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WEDPN16M64V-100B2C 参数 Datasheet PDF下载

WEDPN16M64V-100B2C图片预览
型号: WEDPN16M64V-100B2C
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 16MX64, 7ns, CMOS, PBGA219, 21 X 21 MM, PLASTIC, BGA-219]
分类和应用: 动态存储器内存集成电路
文件页数/大小: 13 页 / 916 K
品牌: MERCURY [ MERCURY UNITED ELECTRONICS INC ]
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WEDPN16M64V-XB2X  
PRELIMINARY  
AC FUNCTIONAL CHARACTERISTICS  
(NOTES 5,6,7,8,9,11)  
Parameter/Condition  
Symbol  
tCCD  
tCKED  
tPED  
-100  
1
-125  
1
-133  
1
Units  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
READ/WRITE command to READ/WRITE command (17)  
CKE to clock disable or power-down entry mode (14)  
CKE to clock enable or power-down exit setup mode (14)  
DQM to input data delay (17)  
1
1
1
1
1
1
tDQD  
tDQM  
tDQZ  
tDWD  
tDAL  
0
0
0
DQM to data mask during WRITEs (17)  
DQM to data high-impedance during READs (17)  
WRITE command to input data delay (17)  
Data-in to ACTIVE command (15)  
0
0
0
2
2
2
0
0
0
4
5
6
Data-in to PRECHARGE command (16)  
Last data-in to burst STOP command (17)  
Last data-in to new READ/WRITE command (17)  
Last data-in to PRECHARGE command (16)  
tDPL  
2
2
2
tBDL  
1
1
1
tCDL  
1
1
1
tRDL  
2
2
2
LOAD MODE REGISTER command to ACTIVE or REFRESH command (24 )  
tMRD  
tROH  
tROH  
2
2
2
CL = 3  
CL = 2  
3
3
3
Data-out to high-impedance from PRECHARGE command (17)  
NOTES  
2
1. All voltages referenced to VSS  
2. This parameter is not tested but garanteed by design. f = 1 MHz, TA = 25°C.  
3. DD is dependent on output loading and cycle rates. Specied values are obtained with minimum  
cycle time and the outputs open.  
.
13. ICC specications are tested after the device is properly initialized.  
14. Timing actually specied by tCKS; clock(s) specied as a reference only at minimum cycle rate.  
15. Timing actually specied by tWR plus tRP; clock(s) specied as a reference only at minimum cycle  
I
rate.  
4. Enables on-chip refresh and address counters.  
16. Timing actually specied by tWR.  
5. The minimum specications are used only to indicate cycle time at which proper operation over  
the full temperature range is ensured.  
17. Required clocks are specied by JEDEC functionality and are not dependent on any timing  
parameter.  
6. An initial pause of 100μs is required after power-up, followed by two AUTO REFRESH  
commands, before proper device operation is ensured. (VCC must be powered up  
simultaneously.) The two AUTO REFRESH command wake-ups should be repeated any time  
the tREF refresh requirement is exceeded.  
18. The ICC current will decrease as the CAS latency is reduced. This is due to the fact that the  
maximum cycle rate is slower as the CAS latency is reduced.  
19. Address transitions average one transition every two clocks.  
20. CLK must be toggled a minimum of two times during this period.  
7. AC characteristics assume tT = 1ns.  
21.  
V
IH overshoot: VIH (MAX) = VCC + 2V for a pulse width 3ns, and the pulse width cannot be  
8. In addition to meeting the transition rate specication, the clock and CKE must transit between  
greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width 3ns.  
V
IH and VIL (or between VIL and VIH) in a monotonic manner.  
22. The clock frequency must remain constant (stable clock is dened as a signal cycling within  
timing constraints specied for the clock pin) during access or precharge states (READ, WRITE,  
including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate.  
23. Auto precharge mode only.  
9. Outputs measured at 1.5V with equivalent load:  
50Ω  
Q
1.5V  
24. Precharge mode only.  
10. tHZ denes the time at which the output achieves the open circuit condition; it is not a reference  
to VOH or VOL. The last valid data element will meet tOH before going High-Z.  
11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover  
point.  
25. JEDEC and PC100 specify three clocks.  
26. Parameter guaranteed by design.  
27. Self refresh avaiable in commercial and industrial temperatures only.  
28. tAC for 100MHz at CL = 3 with no load is 4.6ns and is guaranteed by design.  
12. Other input signals are allowed to transition no more than once every two clocks and are  
otherwise at valid VIH or VIL levels.  
29. Parameter guaranteed by design.  
30. For operating frequencies 45 MHz tCKS = 3.0ns.  
Microsemi Corporation reserves the right to change products or specications without notice.  
July 2011 © 2011 Microsemi Corporation. All rights reserved.  
Rev. 1  
10  
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp  
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