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WE512K8300CM 参数 Datasheet PDF下载

WE512K8300CM图片预览
型号: WE512K8300CM
PDF下载: 下载PDF文件 查看货源
内容描述: [EEPROM Module, 512KX8, 300ns, Parallel, CMOS, CDIP32, HERMETIC SEALED, SINGLE CAVITY, SIDE BRAZED, CERAMIC, DIP-32]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器内存集成电路
文件页数/大小: 14 页 / 1258 K
品牌: MERCURY [ MERCURY UNITED ELECTRONICS INC ]
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WE512K8, WE256K8,  
WE128K8-XCX  
PAGE WRITE OPERATION  
These devices have a page write operation that allows one to 64  
bytes of data (one to 128 bytes for the WE512K8) to be written  
into the device and then simultaneously written during the internal  
programming period. Successive bytes may be loaded in the same  
manner after the rst data byte has been loaded. An internal timer  
begins a time out operation at each write cycle. If another write cycle  
is completed within 150μs or less, a new time out period begins.  
Each write cycle restarts the delay period. The write cycles can be  
continued as long as the interval is less than the time out period.  
The page address must be the same for each byte load and must  
be valid during each high to low transition of WE# (or CS#). The  
block address also must be the same for each byte load and must  
remain valid throughout the WE# (or CS#) low pulse. The page  
and block address lines are summarized below:  
PAGE MODE CHARACTERISTICS  
VCC = 5.0V, VSS = 0V, -55°C TA +125°C  
The usual procedure is to increment the least signicant address  
lines from A0 through A5 (A0 through A6 for the WE512K8) at each  
write cycle. In this manner a page of up to 64 bytes (128 bytes for  
the WE512K8) can be loaded into the EEPROM in a burst mode  
before beginning the relatively long interval programming cycle.  
Parameter  
Write Cycle Time, TYP = 6mS  
Data Set-up Time  
Symbol  
tWC  
Min  
Max  
Unit  
ms  
ns  
10  
tDS  
100  
10  
Data Hold Time  
tDH  
ns  
Write Pulse Width  
tWP  
150  
ns  
After the 150μs time out is completed, the EEPROM begins an  
internal write cycle. During this cycle the entire page of bytes will  
be written at the same time. The internal programming cycle is the  
same regardless of the number of bytes accessed.  
Byte Load Cycle Time  
Write Pulse Width High  
tBLC  
tWPH  
150  
μs  
ns  
50  
Device  
Block Address  
A17-A18  
Page Address  
A7-A16  
WE512K8-XCX  
WE256K8-XCX  
WE128K8-XCX  
A15-A17  
A6-A14  
A15-A16  
A6-A14  
FIGURE 9 – PAGE WRITE WAVEFORMS  
OE#  
CS#  
WE#  
ADDRESS (1)  
DATA  
NOTE:  
1. Decoded Address Lines must be valid for the duration of the write.  
Microsemi Corporation reserves the right to change products or specications without notice.  
August 2011 © 2011 Microsemi Corporation. All rights reserved.  
Rev. 4  
9
Microsemi Corporation • (602) 437-1520 • www.microsemi.com