WE512K8, WE256K8,
WE128K8-XCX
FIGURE 11 –
SOFTWARE DATA PROTECTION
SOFTWARE BLOCK DATA
PROTECTION DISABLE ALGORITHM
A software write protection feature may be enabled or disabled
by the user. When shipped by White Microelectronics, the
devices have the feature disabled. Write access to the device is
unrestricted.
To enable software write protection, the user writes three access
code bytes to three special internal locations. Once write protection
has been enabled, each write to the EEPROM must use the same
three byte write sequence to permit writing. After setting software
data protection, any attempt to write to the device without the
three-byte command sequence will start the internal write timers.
No data will be written to the device, however, for the duration of
tWC. The write protection feature can be disabled by a six byte write
sequence of specific data to specific locations. Power transitions
will not reset the software write protection.
(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
Each 32K byte block (128K bytes for the WE512K8) of EEPROM
has independent write protection. One or more blocks may be
enabled and the rest disabled in any combination. The software
write protection guards against inadvertent writes during
power transitions or unauthorized modification using a PROM
programmer. The block selection is controlled by the upper most
address lines (A17 through A18 for the WE512K8, A15 through A17
for the WE256K8, or A15 and A16 for the WE128K8).
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 20
TO
ADDRESS 5555
EXIT DATA
PROTECT STATE(3)
HARDWARE DATA PROTECTION
Several methods of hardware data protection have been
implemented in the White Microelectronics EEPROM. These are
included to improve reliability during normal operations.
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD LAST BYTE
TO
LAST ADDRESS
a) VCC power on delay
As VCC climbs past 3.8V typical the device will wait
5mSec typical before allowing write cycles.
b) VCC sense
While below 3.8V typical write cycles are inhibited.
c) Write inhibiting
Holding OE# low and either CS# or WE# high inhibits
write cycles.
d) Noise filter
NOTES:
1. Data Format: I/O7-0 (Hex);
Address Format: A14 -A0 (Hex).
Pulses of <8ns (typ) on WE# or CS# will not initiate a
write cycle.
A17 and A18 control selection of one of four blocks in the 512Kx8.
A15, A16, and A17 control selection of one of 8 pages in the 256Kx8.
A15 and A16 control one of the four blocks in the 128Kx8.
2. Write Protect state will be activated at end of write even if no other data is loaded.
3. Write Protect state will be deactivated at end of write period even if no other data
is loaded.
4. 1 to 128 bytes of data at each of 4 blocks may be loaded in the 512Kx8.
1 to 64 bytes of data at each of 8 blocks may be loaded in the 256Kx8 and
1 to 64 bytes on 4 blocks in the 128Kx8.
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 4
11
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
MERCURY [ MERCURY UNITED ELECTRONICS INC ]
