WE128K32-XXX
AC WRITE CHARACTERISTICS
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
WRITE
A write cycle is initiated when OE# is high and a low pulse is on
WE# or CS# with CS# or WE# low. The address is latched on the
falling edge of CS# or WE# whichever occurs last. The data is
latched by the rising edge of CS# or WE#, whichever occurs first.
A byte write operation will automatically continue to completion.
Write Cycle Parameter
Write Cycle Time, TYP = 6ms
Address Set-up Time
Symbol
tWC
Min
Max
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
tAS
0
100
0
Write Pulse Width (WE# or CS#)
Chip Select Set-up Time
Address Hold Time
tWP
tCS
tAH
100
10
0
WRITE CYCLE TIMING
Data Hold Time
tDH
Figures 5 and 6 show the write cycle timing relationships. A write
cycle begins with address application, write enable and chip select.
Chip select is accomplished by placing the CS# line low. Write
enable consists of setting the WE# line low. The write cycle begins
when the last of either CS# or WE# goes low.
Chip Select Hold Time
Data Set-up Time
tCSH
tDS
50
0
Output Enable Set-up Time
Output Enable Hold Time
Write Pulse Width High
tOES
tOEH
tWPH
0
The WE# line transition from high to low also initiates an internal
150 μsec delay timer to permit page mode operation. Each
subsequent WE# transition from high to low that occurs before the
completion of the 150 μsec time out will restart the timer from zero.
The operation of the timer is the same as a retriggerable one-shot.
50
4
4315.19E-0718-ss-WE128K32-XXX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
MERCURY [ MERCURY UNITED ELECTRONICS INC ]
