W3E64M72S-XSBX
White Electronic Designs
DENSITY COMPARISONS
ACTUAL SIZE
25
White Electronic Designs
W3E64M72S-XSBX
32
Area = 800mm2
I/O Count = 219 Balls
SAVINGS – Area: 66% – I/O Count: 55%
Discrete Approach
11.9
11.9
11.9
11.9
11.9
11.9
11.9
11.9
11.9
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
22.3
Area: 9 x 265mm2 = 2,385mm2
I/O Count: 9 x 54 pins = 486 pins
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed. The address bits registered
coincident with the READ or WRITE command are used
to select the bank and the starting column location for the
burst access.
saving power-down mode. All inputs are compatible with
the Jedec Standard for SSTL_2. All full drive options
outputs are SSTL_2, Class II compatible.
FUNCTIONAL DESCRIPTION
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with theACTIVE command are used to select the bank and
row to be accessed (BA0 and BA1 select the bank, A0-12
select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst access.
The pipelined, multibank architecture of DDR SDRAMs allows
for concurrent operation, thereby providing high effective
bandwidth by hiding row precharge and activation time.
Prior to normal operation, the DDR SDRAM must be
initialized. The following sections provide detailed
information covering device initialization, register definition,
command descriptions and device operation.
An auto refresh mode is provided, along with a power-
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September 2007
Rev. 3
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
MERCURY [ MERCURY UNITED ELECTRONICS INC ]
