W3E32M64S-XBX
White Electronic Designs
and QFC. These functions are controlled via the bits shown
COMMANDS
in Figure 5. The extended mode register is programmed
via the LOAD MODE REGISTER command to the mode
register (with BA0 = 1 and BA1 = 0) and will retain the
stored information until it is programmed again or the
device loses power. The enabling of the DLLshould always
be followed by a LOAD MODE REGISTER command to the
mode register (BA0/BA1 both LOW) to reset the DLL.
The Truth Table provides a quick reference of available
commands. This is followed by a written description of
each command.
DESELECT
The DESELECT function (CS# High) prevents new
commands from being executed by the DDR SDRAM. The
SDRAM is effectively deselected. Operations already in
progress are not affected.
TABLE 2 – CAS LATENCY
ALLOWABLE OPERATING
FREQUENCY (MHz)
NO OPERATION (NOP)
Data Rate
-200
CAS LATENCY = 2
CAS LATENCY = 2.5
≤ 75
≤ 100
≤ 100
-
≤ 100
≤ 125
≤ 133
≤ 166
The NO OPERATION (NOP) command is used to perform
a NOP to the selected DDR SDRAM (CS# is LOW while
RAS#, CAS#, and WE# are high). This prevents unwanted
commands from being registered during idle or wait states.
Operations already in progress are not affected.
-250
-266
-333
The extended mode register must be loaded when all
banks are idle and no bursts are in progress, and the
controller must wait the specified time before initiating
any subsequent operation. Violating either of these
requirements could result in unspecified operation.
LOAD MODE REGISTER
The Mode Registers are loaded via inputs A0-12. The
LOAD MODE REGISTER command can only be issued
when all banks are idle, and a subsequent executable
command cannot be issued until tMRD is met.
OUTPUT DRIVE STRENGTH
ACTIVE
The normal full drive strength for all outputs are specified to
be SSTL2, Class II. The DDR SDRAM supports an option
for reduced drive. This option is intended for the support
of the lighter load and/or point-to-point environments. The
selection of the reduced drive strength will alter the DQs
and DQSs from SSTL2, Class II drive strength to a reduced
drive strength, which is approximately 54 percent of the
SSTL2, Class II drive strength.
The ACTIVE command is used to open (or activate) a
row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputsA0-12 selects the row. This row
remains active (or open) for accesses until a PRECHARGE
command is issued to that bank. A PRECHARGE
command must be issued before opening a different row
in the same bank.
DLL ENABLE/DISABLE
READ
When the part is running without the DLL enabled, device
functionality may be altered. The DLL must be enabled for
normal operation. DLL enable is required during power-
up initialization and upon returning to normal operation
after having disabled the DLL for the purpose of debug or
evaluation. (When the device exits self refresh mode, the
DLLis enabled automatically.)Any time the DLLis enabled,
200 clock cycles with CKE high must occur before a READ
command can be issued.
The READ command is used to initiate a burst read access
to an active row. The value on the BA0, BA1 inputs selects
the bank, and the address provided on inputsA0-9 selects
the starting column location. The value on input A10
determines whether or notAUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed
will be precharged at the end of the READ burst; if AUTO
PRECHARGE is not selected, the row will remain open
for subsequent accesses.
February 2007
Rev. 4
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
MERCURY [ MERCURY UNITED ELECTRONICS INC ]
