EDI88128CS
AC CHARACTERISTICS – READ CYCLE (15 to 20ns)
VCC = 5.0V, Vss = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Units
Symbol
15ns*
17ns
20ns
JEDEC
Alt.
tRC
Min
Max
Min
Max
Min
Max
Read Cycle Time
tAVAV
tAVQV
tELQV
tELQX
tEHQZ
tAVQX
tGLQV
tGLQX
tGHQZ
tELICCH
tEHICCL
15
17
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tAA
15
15
17
17
20
20
Chip Enable Access Time
tACS
tCLZ
tCHZ
tOH
Chip Enable to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z(1)
Chip Enable to Power Up (1)
Chip Enable to Power Down (1)
3
0
0
0
3
0
0
0
3
0
0
0
8
6
8
6
10
8
tOE
tOLZ
tOHZ
tPU
6
6
8
tPD
15
17
20
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS – READ CYCLE (25 to 55ns)
VCC = 5.0V, Vss = 0V, -55°C ≤ TA ≤ +125°C
Symbol
25ns
35ns
45ns
55ns
Parameter
JEDEC
Alt.
tRC
Min
Max
Min
Max
Min
Max
Min
Max
Units
ns
Read Cycle Time
tAVAV
tAVQV
tELQV
tELQX
tEHQZ
tAVQX
tGLQV
tGLQX
tGHQZ
tELICCH
tEHICCL
25
35
45
55
Address Access Time
tAA
25
25
35
35
45
45
55
55
ns
Chip Enable Access Time
tACS
tCLZ
tCHZ
tOH
ns
Chip Enable to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z(1)
Chip Enable to Power Up (1)
Chip Enable to Power Down (1)
3
0
0
0
3
0
0
0
3
0
0
0
3
0
0
0
ns
12
10
10
25
20
15
15
35
20
20
20
45
20
25
20
55
ns
ns
tOE
ns
tOLZ
tOHZ
tPU
ns
ns
ns
tPD
ns
1. This parameter is guaranteed by design but not tested.
AC TEST CONDITIONS
Figure 1
Figure 2
Vcc
Vcc
Input Pulse Levels
Input Rise and Fall Times
VSS to 3.0V
480Ω
480Ω
5ns
1.5V
Input and Output Timing Levels
Output Load
Q
Q
Figure 1
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2
30pF
5pF
255Ω
255Ω
3
4249.14E-0816-ss-EDI88128CS
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com