EVB72016
433MHz FSK/ASK Transmitter
Evaluation Board Description
2.8 Mode Control Logic
The mode control logic allows two different
modes of operation as listed in the following
table. The mode control pin EN is pulled-down
internally. This guarantees that the whole circuit
is shut down if this pin is left floating.
EN
0
Mode
Description
TX standby
TX disabled
1
TX active
CKOUT active
TX / CKOUT
enabled
2.9 Clock Output
The clock output CKOUT is CMOS-compatible and can be used to drive a microcontroller. The frequency of
the clock can be changed by the clock divider control signal CKDIV, that can be selected according to the
following table. A capacitor at pin CKOUT can be used to control the clock voltage swing and the spurious
emission.
CKDIV
Clock divider ratio
Clock frequency / fc=433.92 MHz
0
1
4
3.39 MHz
848 kHz
16
2.10 Timing Diagrams
After enabling the transmitter by the EN signal, the power amplifier remains inactive for the time ton, the
transmitter start-up time. The crystal oscillator starts oscillation and the PLL locks to the desired output fre-
quency within the time duration ton. After successful PLL lock, the LOCK signal turns on the power amplifier,
and then the RF carrier can be FSK or ASK modulated.
high
EN
low
high
EN
low
high
high
LOCK
LOCK
low
low
high
high
FSKDTA
PSEL
low
low
RF carrier
t
t
t
t
on
on
Fig. 5: Timing diagrams for FSK and ASK modulation
For more detailed information, please refer to the latest TH72016 data sheet revision.
3901272016 01
Rev. 004
Page 6 of 12
EVB Description
June/07
MELEXIS [ Melexis Microelectronic Systems ]
