EVB71122
300 to 930MHz Receiver
Evaluation Board Description
2.2.5
PLL Counter Ranges
In order to cover the frequency range of about 300 to 930MHz the following counter values are implemented
in the receiver:
PLL Counter Ranges
A
N
R
P
0 to 31 (5bit)
3 to 2047 (11bit)
3 to 2047 (11bit)
32
Therefore the minimum and maximum divider ratios of the PLL feedback divider are given by:
Ntotmin = 32⋅32 = 1024
Ntotmax = 2047⋅32 + 31 = 65535
2.3 SPI Description
2.3.1
General
Serial programming interface (SPI) mode can be activated by choosing SPISEL = 1 (e.g. at positive supply
voltage VCC). In this mode, the input pins 17, 18 and 19 are used as a 3-wire unidirectional serial bus inter-
face (SDEN, SDTA, SCLK). The internal latches contain all user programmable variables including counter
settings, mode bits etc.
In addition the MFO pin can be programmed as an output (see section 4.1.4) in order to read data from the
internal latches and it can be used as an output for different test modes as well.
At each rising edge of the SCLK signal, the logic value at the SDTA terminal is written into a shift register.
The programming information is taken over into internal latches with the rising edge of SDEN. Additional
leading bits are ignored, only the last bits are serially clocked into the shift register. A normal write operation
shifts 16 bits into the SPI, a normal read operation shifts 4 bits into the SPI and reads additional 12 bits from
the MFO pin. If less than 12 data bits are shifted into SDTA during the write operation then the control regis-
ter may contain invalid information.
In general a control word has the following format. Bit 0 is the Read/Write bit that determines whether it is a
read (R/W = 1) or a write (R/W = 0) sequence. The R/W bit is preceding the latch address and the
corresponding data bits.
Control Word Format
MSB
LSB
MSB
LSB
Bit 0
Data
D6 D5
Latch Address Mode
A2 A2 A0 R/W
D11 D10 D9
D8
D7
D4
D3
D2
D1
D0
There are two control word formats for read and for write operation. Data bits are only needed in write mode.
Read operations require only a latch address and a R/W bit.
Due to the static CMOS design, the serial interface consumes virtually no current. The SPI is a fully separate
building block and can therefore be programmed in every operational mode.
39012 71122 01
Rev. 001
Page 11 of 32
EVB Description
Sept/06
MELEXIS [ Melexis Microelectronic Systems ]
