EVB71122
300 to 930MHz Receiver
Evaluation Board Description
3.1.2
Control Word R1
Name
Bits
Description
charge pump current setting
#default
00
01
10
11
100µA
400µA
400µA static down
400µA static up
CPCUR
[1:0]
PFD output polarity
lock detector time error
lock detection time
[2]
[3]
PFDPOL
LDERR
0
1
negative
positive
#default
#default
0
1
15ns
30ns
00
01
10
11
2/fR
4/fR
8/fR
[5:4]
LDTIME
#default
#default
16/fR
minimum time span before lock in
fR is the reference oscillator frequency fRO divided by R, see section 4.1.5 (R4)
lock detector mode
LDMODE
[6]
[7]
0
1
check lock condition permanently
check lock condition until 1st lock in
VCO range
0
1
3V supply
5V supply
VCORANGE
#default
#default
#default
#default
VCO range setting for different VCCs.
VCO core current
VCOCUR
VCOBUF
[8]
[9]
0
1
450µA
520µA
VCO buffer current
0
1
900µA
1040µA
prescaler 32/33 reference current
0
1
20µA
30µA
PRESCUR
SHOWLD
[10]
[11]
30µA may be used for fRF = 868/915MHz
function of LDRSSIL bit
0
1
RSSIL (RSSI low flag)
LD (lock detection flag)
#default
select output data of LDRSSIL, see section 4.1.8 (R7)
39012 71122 01
Rev. 001
Page 16 of 32
EVB Description
Sept/06
MELEXIS [ Melexis Microelectronic Systems ]
