Nonvolatile Registers:
There are two Nonvolatile Registers named
OR0
and
OR1
individually. They are designed
to configure the MPC89x515A options.
Generally these two nonvolatile registers will be written via a popular NVM writer, say Hi-Lo System
All-11, Labtool-48 and Megawin-Provided MCU writer. Furthermore, the user can change the NVM
register
OR1
by the ISP program, but
OR0
can only be written via an off-line popular NVM writer.
NVM register: OR0
(Option
Register 0):
Bit-7
-
Bit-6
-
Bit-5
ISPAS1
Bit-4
ISPAS0
Bit-3
-
Bit-2
MOVCL
Bit-1
SB
Bit-0
LOCK
{ISPAS1,
ISPAS0}:
Used to identify the start address for ISP program
{0,
0}:
= The ISP space is from 0xEC00 to 0xFBFF (4K size).
{0,
1}:
= The ISP space is from 0xF400 to 0xFBFF (2K size).
{1,
0}:
= The ISP space is from 0xF800 to 0xFBFF (1K size)
{1,
1}:
= No ISP space.
These two bits decide where the ISP program locates.
MOVCL:
Used to determine if MOVC instruction will be disabled.
0:=
MOVC is conditionally disabled.
1:=
MOVC is always available.
SB:
Used to determine if the program code will be scrambled while it is dumped.
0:=
Code dump from Writer is scrambled.
1:=
Code dump from Writer is transparent.
LOCK:
Used to determine if the program code will be locked against the popular writer.
0:=
lock code.
1:=
does not lock code
If the code is locked, all the data dumped from a popular will always show
FFh.
Please check file initial Configuration.pdf to get the default value of the OR0.
10
MPC89x515A Data Sheet
MEGAWIN
MEGAWIN [ MEGAWIN TECHNOLOGY CO., LTD ]
