IP (or XICON) and IPH are combined to form 4-level priority interrupt as the following table.
Priority
{IPH.x , IP.x}
Level
11
10
01
00
1 (highest)
2
3
4
SFR: XICON (External Interrupt Control):
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
PX3
EX3
IE3
IT3
PX2
EX2
IE2
IT2
PX3 : If set, Set priority for external interrupt 3 higher
EX3 : If set, Enables external interrupt 3.
IE3 : Interrupt 3 Edge flag. Sets by hardware when external interrupt edge detected. Cleared when
interrupt processed.
IT3 : Interrupt 3 type control bit. Set/Cleared by software to specified falling edge/low level triggered
interrupt.
PX2 : If set, Set priority for external interrupt 3 higher
EX2 : If set, enables external interrupt 2.
IE2 : Interrupt 2 Edge flag. Sets by hardware when external interrupt edge detected. Cleared when
interrupt processed.
IT2 : Interrupt 2 types control bit. Set/Cleared by software to specify falling edge/low level triggered
interrupt.
Watchdog Timer
CLK/12
8
8-bit pre-scalar timer
ENW
15-bit WDT
RESET
PS0
IDLE
PS1
WIDL
PS2
CLRW
22
MPC89x515A Data Sheet
MEGAWIN
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