MPC89x51A carried with convenient mechanism to help the user read/change the flash content.
Just filling the target address and data into several SFR, and triggering the built-in ISP
automation, the user can easily erase, read, and program the embedded flash and option
registers OR1.
There are several SFR designed to help the user implement the ISP functionality.
SFR: IFD (ISP Flash Data register):
Bits-7
Bits-6
Bits-5
Bits-4
Bits-3
Bits-2
Bits-1
Bits-0
(Data to be written into flash, or data got from flash)
IFD is the data port register for ISP operation. The data in IFD will be written into the desired address in
operating ISP write and it is the data window of readout in operating ISP read.
SFR: IFADRH (ISP Flash Address High):
Bits-7
Bits-6
Bits-5
Bits-4
Bits-3
Bits-2
Bits-1
Bits-0
Bits-0
Bits-0
(High bytes of the address pointing to flash memory)
IFADRH is the high-bytes address port for all ISP modes.
SFR: IFADRL (ISP Flash Address Low):
Bits-7
Bits-6
Bits-5
Bits-4
Bits-3
Bits-2
Bits-1
(Low bytes of the address pointing to flash memory)
IFADRL is the low-bytes address port for all ISP modes.
SFR: IFMT (ISP Flash Mode Table):
Bits-7
Bits-6
Bits-5
Bits-4
Bits-3
Bits-2
Bits-1
reserved
Mode Selection
Mode Selection
To Operate
0
0
0
0
1
1
1
0
0
1
1
1
0
1
0
1
0
1
1
1
0
Standby
AP-memory read
AP-memory/Data-flash program
AP-memory/Data-flash page erase
OR1 memory erase (IFADRL[0]=1).
OR1 memory read ( IFADRL[0] =1)
OR1 memory program ( IFADRL[0] = 1)
Note: OR0 cannot be changed by ISP operation. It can be accessed only by Writer. Only OR1 can be
changed by ISP program.
SFR: SCMD (Sequential Command Data register for ISP) :
28
MPC89x51A Data Sheet
MEGAWIN
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