Functional Description
I/O Port Configuration
All 27 port pins on MPC82x54A may be independently configured to one of four modes:
quasi-bidirectional (standard 8051 port output), push-pull output, open-drain output or
input-only. All port pins default to quasi-bidirectional after reset. Each port pin has a
Schmitt-triggered input for improved input noise rejection. During power-down, all the
Schmitt-triggered inputs are disabled with the exception of P3.2 and P3.3, which may be used
to wake-up the device. Therefore P3.2 and P3.3 should not be left floating during
power-down.
There are several special function registers designed to configure those I/O ports.
SFR:
P0M0
(P0 Configuration 0)
Bit-7
-
Bit-6
-
Bit-5
-
Bit-4
-
Bit-3
P0M03
Bit-2
P0M02
Bit-1
P0M01
Bit-0
P0M00
SFR:
P0M1
(P0 Configuration 1)
Bit-7
-
Bit-6
-
Bit-5
-
Bit-4
-
Bit-3
P0M13
Bit-2
P0M12
Bit-1
P0M11
Bit-0
P0M10
SFR:
P1M0
(P1 Configuration 0)
Bit-7
P1M07
Bit-6
P1M06
Bit-5
P1M05
Bit-4
P1M04
Bit-3
P1M03
Bit-2
P1M02
Bit-1
P1M01
Bit-0
P1M00
SFR:
P1M1
(P1 Configuration 1)
Bit-7
P1M17
Bit-6
P1M16
Bit-5
P1M15
Bit-4
P1M14
Bit-3
P1M13
Bit-2
P1M12
Bit-1
P1M11
Bit-0
P1M10
SFR:
P2M0
(P2 Configuration 0)
Bit-7
P2M07
Bit-6
P2M06
Bit-5
P2M05
Bit-4
P2M04
Bit-3
P2M03
Bit-2
P2M02
Bit-1
P2M01
Bit-0
P2M00
SFR:
P2M1
(P2 Configuration 1)
Bit-7
P2M17
Bit-6
P2M16
Bit-5
P2M15
Bit-4
P2M14
Bit-3
P2M13
Bit-2
P2M12
Bit-1
P2M11
Bit-0
P2M10
SFR:
P3M0
(P3 Configuration 0)
Bit-7
P3M07
Bit-6
P3M06
Bit-5
P3M05
Bit-4
P3M04
Bit-3
P3M03
Bit-2
P3M02
Bit-1
P3M01
Bit-0
P3M00
20
MPC82x54A Data Sheet
MEGAWIN
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