Mode Selection
To Operate
0
0
1
1
0
1
0
1
Standby
AP-memory read
AP-memory/Data-flash program
AP-memory/Data-flash page erase
SFR: SCMD (ISP Sequential Command register to trigger ISP/IAP operation)
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
/ Device ID
Bit-2
Bit-1
Bit-0
ISP-Command
SCMD is the command port for triggering ISP activity. If SCMD is filled with sequential 46H, B9H and if
ISPCR.7 = 1, ISP activity will be triggered.
When this register is read, the device ID of MPC82x54A will be returned (2 bytes). The MSB byte of
this device ID is F3H and LSB byte 04H. IFADRL.0 is used to select HIGH/LOW byte of the device ID.
SFR: ISPCR (ISP Control register)
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
ISPEN
SWBS
SWRST
CFAIL
-
WAIT
ISPEN:= Determine if to Enable ISP/IAP functionality
0: =
Disable ISP program to change flash.
1: =
Enable ISP program to change flash.
SWBS:= Software Boot entrance Selector
0: =
Boot from main-memory.
1: =
Boot from ISP memory.
Note: This bit will be loaded with HWBS(OR0.3) after power-up moment.
SWRST:= Software Reset trigger
Setting this bit will cause the device reset.
CFAIL:= ISP/IAP Command Fail flag
0: =
The last ISP/IAP command has finished successfully.
1: =
The last ISP/IAP command fails. It could be caused since the access of flash memory
was inhibited.
WAIT:= Waiting time selection while the flash is busy.
CPU Wait time (Oscillator cycle)
ISPCR[2:0]
Page Erase
Program
Read
Recommended
System clock
30M~24M
24M~20M
20M~12M
12M~6M
6M~3M
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
672384
504288
420240
252144
126072
63036
1760
1320
1100
660
330
165
110
2
2
2
2
2
2
2
2
3M~2M
2M~1M
< 1M
42024
21012
55
Notice: Software reset actions could reset other SFR, but it never influences bits ISPEN and SWBS.
The ISPEN and SWBS only will be reset by power-up action, while not software reset.
MEGAWIN
MPC82x54A Data Sheet
61
MEGAWIN [ MEGAWIN TECHNOLOGY CO., LTD ]
