Analog to Digital Converter
ADCTL Register
ADCON
SPEED1 SPEED0
ADCI ADCS CHS2 CHS1 CHS0
ADCV Register
B4 B3
P1.7(AIN7)
P1.6(AIN6)
B7
B6
B5
B2
B1
B0
P1.5(AIN5)
P1.4(AIN4)
P1.3(AIN3)
P1.2(AIN2)
P1.1(AIN1)
P1.0(AIN0)
+
-
Successive
Approximation
Regiter
Comparator
8-bit DAC
8
The ADC on MPC82x52A is an 8-bit resolution, successive-approximation approach, and
medium-speed A/D converter. VREFP / VREFM is the positive/negative reference voltage input for
internal voltage-scaling DAC use, and the typical sink current on it is 600uA ~ 1mA. For
MPC82x52A, these two references are internally tied to VDD and GND, separately.
Conversion is invoked since ADCS bit is set. Prior to ADC conversion, the desired I/O ports for
analog inputs should be configured as input-only or open-drain mode first. The conversion
takes around a fourth cycles to sample analog input data and other three fourths cycles in
successive-approximation steps. Total conversion time is controlled by two register bits –
SPEED1 and SPEED0. Analog input source comes from P1, and one of the eight-channels is
multiplexed by analog multiplexer into the comparator. When conversion is completed, the
result will be saved onto ADCV register. After the result has been loaded onto ADCV register,
ADCI will be set. ADCI associated with its enable register AUXR.4 (EADCI), shares ESPI bit
with SPI block to control the interrupt. ADCI should be cleared in software. The ADC interrupt
service routine vectors to 2BH . When the chip enters idle mode or power-down mode, the
power of ADC is turned off by hardware.
Vin – VREFM
ADCV
= 256 x
VREFP - VREFM
54
MPC82x52A Data Sheet
MEGAWIN
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