Watch Dog Timer
The watch dog timer in MPC82x52A consists of an 8-bit pre-scalar timer and a 15-bit timer.
The timer is one-time enabled by setting ENW. Clearing ENW can not stop WDT counting.
When the WDT is enabled, software should always reset the timer by writing 1 to CLRW bit
before the WDT overflows. If MPC82x52A is out of control by any disturbance, that means the
CPU can not run the software normally then WDT may miss the “writing 1 to CLRW”, and
overflow will come. WDT overflow reset the CPU to restart. Associated with the WDTCR
SFR, a NVM option register bytes named OR3 are designed to enable WDT, and initiate
WDTCR with initial states. See Option Register description to know in more details.
1/256
1/128
1/64
1/32
1/16
15-bit timer
1/8
1/4
1/2
8-bit prescalar
Fosc/12
IDLE
CLRW
WRF
-
ENW
WIDL PS2 PS1
PS0
WDTCR Register
To make good use of the watch-dog-timer, the user should take notice on SFR WDTCR.
SFR: WDTCR (WDT Control Register)
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
WRF
-
ENW
CLRW
WIDL
PS2
PS1
PS0
WRF: = When WDT overflows, this bit is set. It can be cleared by software.
ENW: = Control bit to enable Watch-Dog-Timer. (One-time enabled, can not be disabled)
0: = (default)
Disable Watch Dog Timer
1: =
Enable Watch Dog Timer start counting
CLRW: = Set this bit to recount WDT. Hardware will automatically clear this bit.
MEGAWIN
MPC82x52A Data Sheet
33
MEGAWIN [ MEGAWIN TECHNOLOGY CO., LTD ]
