18.2 WDT Operation
The WDT is by default disabled after power-on reset. To enable the WDT, the user must set the ENW bit. When
the WDT is enabled, the user needs to service it by setting the CLW bit to clear the WDT counter and avoid an
overflow. The 15-bit WDT counter will overflow when it reaches 32767 (7FFFH) and this will reset the device. And,
when the WDT is enabled, it will increment every 12 system clock cycles (12/Fosc) while the oscillator is running.
This means the user must clear the WDT counter at least every 32767 x12 system cock cycles.
The WDT in this device is one-time enabled. The so-called “one-time enabled” means: Once the WDT is enabled
by setting ENW bit, there is no way to disable it except through power-on reset, which will clear the ENW bit. And,
the WDTCR register will keep the previous programmed value unchanged after any resets (including hardware
reset, software reset and WDT reset) except the power-on reset. For example, if the WDTCR is 0x2D, it still
keeps at 0x2D rather than 0x00 after resets. Only power-on reset can initialize it to 0x00. In other words, the
WDT can only be disabled by a power-on reset. Thus it is called “one-time enabled” WDT.
The WDT overflow period is determined by the formula:
215 x Prescaler x (12 / Fosc)
Table 18-1 shows the WDT overflow period for MCU running at 6/12/24MHz. The period is the maximum interval
for the user to clear the WDT to prevent from chip reset.
Table 18-1. WDT Overflow Period
PS2 PS1 PS0
Prescaler value
Fosc=6MHz
131.072 ms
262.144 ms
524.288 ms
1.048 s
Fosc=12MHz
65.536 ms
131.072 ms
262.144 ms
524.288 ms
1.048 s
Fosc=24MHz
32.768 ms
65.536 ms
131.072 ms
262.144 ms
524.288 ms
1.048 s
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
4
8
16
32
64
128
256
2.097 s
4.194 s
2.097 s
8.389 s
4.194 s
2.097 s
16.778 s
8.389 s
4.194 s
18.3 Sample Code for WDT
Condition: WDT Overflow Period = 1.048 seconds @Fosc=12MHz
WDTCR_buf DATA 30h
;declare a buffer for WDTCR register
;(because WDTCR is a Write-only register)
start:
;...
MOV
WDTCR_buf,#00h ;initialize the WDTCR buffer
WDTCR_buf,#04h ;PS2=1
WDTCR_buf,#0FCh ;PS1=0,PS0=0
WDTCR,WDTCR_buf ;write to WDTCR Î(PS2,PS1,PS0)=(1,0,0), prescaler=32
ORL
ANL
MOV
ORL
MOV
WDTCR_buf,#20h ;ENW=1
WDTCR,WDTCR_buf ;write to WDTCR register Îenable WDT
main_loop:
ORL
WDTCR_buf,#10h ;CLRW=0
MOV
WDTCR,WDTCR_buf ;write to WDTCR register Îclear WDT counter
;...
;...
JMP
main_loop
87
MPC82G516A Data Sheet
MEGAWIN
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