Serial Peripheral Interface (SPI)
The device provides another high-speed serial communication interface, the SPI interface.
The SPI is a full-duplex, high-speed, synchronous communication bus with two operation
modes:
Master
mode and
Slave
mode. Up to 3Mbit/s can be supported in either
Master
or
Slave
mode under the Fosc=12MHz. Two status flags are provided to signal the transfer
completion and write-collision occurrence.
Shift In Register
Clock Divider
Fosc
4,
16,
64
128
Shift Out Register
I/O control
P1.6
(MISO)
P1.5
(MOSI)
P1.7
(SPICLK)
SPI Control
P1.4
(SS)
SSIG
SPEN DORD MSTR
CPOL CPHA SPR1
SPR0
SPICTL
SPIF
WCOL
-
-
-
-
-
-
SPISTAT
SPI block diagram
There are three pins implementing the SPI functionality. One of them is SPICLK (P1.7), next is
MISO (P1.6), and the last is MOSI (P1.5). An extra pin SS (P1.4) is designed to configure the
SPI to run under
Master
or
Slave
mode. Data flows from master to slave via MOSI (Master
Out Slave In) pin, and flows from slave to master via MISO (Master In Slave Out) pin. The
SPICLK plays as an output pin when the device works under
Master
mode. At the same time,
as an input pin when the device works under
Slave
mode. If the SPI system is disabled, i.e.,
SPEN
(SPICTL.6) =0, these pins are configured as general-purposed I/O port (P1.4 ~ P1.7).
Two devices with SPI interface communicate with each other via one synchronous clock
signal, i.e., one input data signal, and one output data signal. There are two concerns the user
could take care. One of them is latching data on the negative edge or positive edge of the
clock signal which named
polarity.
And the other is keeping the clock signal low or high while
the device idle which named
phase.
Permuting those states from
polarity
and
phase,
there
MEGAWIN
MPC82x54A Data Sheet
47
MEGAWIN [ MEGAWIN TECHNOLOGY CO., LTD ]
