Communication
In SPI, transfers are always initiated by the master. If the SPI is enabled(SPEN=1) and
selected as master, any instruction that use SPI data register SPIDAT as the destination will
starts the SPI clock generator and a data transfer. The data will start to appear on MOSI about
one half SPI bit-time to one SPI bit-time after it. Before starting the transfer, the master may
select a slave by driving the SS pin of the corresponding device low. Data written to the
SPIDAT register of the master shifted out of MOSI pin of the master to the MOSI pin of the
slave. And at the same time the data in SPIDAT register of the selected slave is shifted out of
MISO pin to the MISO pin of the master. During one byte transfer, data in the master and in
the slave is interchanged. After shifting one byte, the transfer completion flag (SPIF) is set and
an interrupt will be created if the SPI interrupt is enabled.
If SPEN=1, SSIG=0, SS pin=1 and MSTR=1, the SPI is enabled in master mode. Before the
instruction that use SPIDAT as the destination register, the master is in idle state and can be
selected as slave device by any other master drives the idle master SS pin low. Once this
happened, MSTR bit of the idle master is cleared by hardware and changes its state a
selected slave. User software should always check the MSTR bit. If this bit is cleared by the
mode change of SS pin, and if the user wants to continue to use the SPI as a master later, the
user must set the MSTR bit again, or otherwise it will always stay in slave mode.
The SPI is single buffered in transmit direction and double buffered in receive direction. New
data for transmission can not be written to the shift register until the previous transaction is
complete. The WCOL bit is set to signal data collision when the data register is written during
transaction. In this case, the data currently being transmitted will continue to be transmitted,
but the new data which causing the collision will be lost. For receiving data, received data is
transferred into a internal parallel read data buffer so that the shift register is free to accept a
second byte. However, the received byte must be read from the data register (SPIDAT) before
the next byte has been completely transferred. Otherwise the previous byte is lost. WCOL can
be cleared in software by “writing 1 to the bit”.
MEGAWIN
MPC82x52A Data Sheet
51
MEGAWIN [ MEGAWIN TECHNOLOGY CO., LTD ]
