SFR: ADCTL (ADC Control register)
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
ADCON
SPEED1
SPEED0
ADCI
ADCS
CHS2
CHS1
CHS0
ADCON :=
When clear shut down the power of ADC block. When set turn on the power
of ADC block.
{SPEED1, SPEED0}:= Conversion speed selector
{0,0}:= (default)
A conversion takes 1080 clock cycles
{0,1}:=
A conversion takes 810 clock cycles
{1,0}:=
A conversion takes 540 clock cycles
{1,1}:=
A conversion takes 270 clock cycles
ADCS := ADC Start control
Set to start an A/D conversion. It will be automatically cleared by the device
after the device has finished the conversion.
ADCI := ADC Interrupt flag
It will be set by the device after the device has finished a conversion, and
should be cleared by the user’s software.
{CHS2, CHS1, CHS0} := Input Channel Selector
{0,0,0}:= (default)
Set P1.0 as the A/D channel input
{0,0,1}:=
Set P1.1 as the A/D channel input
{0,1,0}:=
Set P1.2 as the A/D channel input
{0,1,1}:=
Set P1.3 as the A/D channel input
{1,0,0}:=
Set P1.4 as the A/D channel input
{1,0,1}:=
Set P1.5 as the A/D channel input
{1,1,0}:=
Set P1.6 as the A/D channel input
{1,1,1}:=
Set P1.7 as the A/D channel input
SFR: ADCV (ADC Result Register):
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
ADCV.9
ADCV.8
ADCV.7
ADCV.6
ADCV.5
ADCV.4
ADCV.3
ADCV.2
SFR: ADCVL (ADC Result Low):
Bit-7
-
Bit-6
-
Bit-5
-
Bit-4
-
Bit-3
-
Bit-2
-
Bit-1
Bit-0
ADCV.1
ADCV.0
The {ADCV[7:0], ADCVL[1:0]} is the final result from the A/D conversion.
MEGAWIN
MPC82x54A Data Sheet
55
MEGAWIN [ MEGAWIN TECHNOLOGY CO., LTD ]
