could be four modes formed, they are SPI-MODE-0, SPI-MODE-1, SPI-MODE-2, and
SPI-MODE-3. Many device declares that they meet SPI mechanism, but few of them are
adaptive to all four modes. The MPC82x54A is flexible enough to be configured to
communicate to another device with MODE-0, MODE-1, MODE-2 or MODE-3 SPI, and play
part of Master and Slave.
There is a SFR named SPICTL designed to configure the SPI behavior of the device.
SFR: SPICTL (SPI Control register)
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
SSIG
SPEN
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
SSIG: = used to determine if Ignore the pin SS
0: = (default)
Reserve the function of pin SS
1: =
Ignore the SS pin function
SPEN: = Enable the SPI
0: = (default)
Disable the SPI function. All related pins play as general-purposed I/O ports.
1: =
Enable the SPI function.
DORD: = Data Order
0: = (default)
Transmit/Receive the MSB of the data byte first.
1: =
Transmit/Receive the LSB of the data byte first.
MSTR: = Set to Master mode
0: = (default)
Set the SPI to play as Slave part.
1: =
Set the SPI to play as Master part.
CPOL: = Clock Polarity
0: = (default)
Set the SPICLK as LOW while the communication is kept idle. That implies the leading
edge of the clock is the rising edge, and the trailing edge is the falling edge.
1: =
Set the SPICLK as HIGH while the communication is kept idle. That implies the leading
edge of the clock is the falling edge, and the trailing edge is the falling rising edge.
CPHA: = Clock Phase
0: = (default)
Data is driven when pin SS is low and changes on the trailing edge of SPICLK,
and is sampled on the leading edge. (This setting is only valid while SSIG==0.)
1: =
Data is driven on the leading edge of SPICLK, and is sampled on the trailing edge.
{SPR1, SPR0}: = SPI clock Rate selector
{0,0}: = (default)
Set the clock rate of the SPI as the frequency of the clock source over 4.
{0,1}: =
Set the clock rate of the SPI as the frequency of the clock source over 16.
48
MPC82x54A Data Sheet
MEGAWIN
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