High Speed Output Mode
In this mode, the CEXn output (port latch) associated with the PCA module will toggle each
time a match occurs between the PCA counter and the module’s capture registers. To activate
this mode the TOGn, MATn, and ECOMn bits in the SFR CCAPMn must be set.
Pulse Width Modulator Mode
All of the PCA modules can be used as PWM outputs. The frequency of the output depends
on the PCA counter. All of the modules will have the same frequency of output because they
all share the PCA counter. The duty cycle of each module is independently variable using the
module’s capture register CCAPnL [7:0] and bits EPCnL in SFR PCAPWMn. When the value
of the SFR CL is less than the value in the module’s {EPCnL, CCAPnL [7:0]}, the output will
be low. When it is equal to or greater than, the output will be high. When CL overflows from
FFH to 00H, {EPCnL, CCAPnL [7:0]} is reloaded with the value in {EPCnH, CCAPnH [7:0]}.
That allows smoothly updating the PWM duty without glitches. The bits PWMn and ECOMn
bits in the CCAPMn must be set to enable the PWM mode.
SFR: PCAPWM0 (PCA PWM Mode Auxiliary Register 0 )
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
-
-
-
-
-
-
EPC0H
EPC0L
SFR: PCAPWM1 (PCA PWM Mode Auxiliary Register 1)
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
-
-
-
-
-
-
EPC1H
EPC1L
SFR: PCAPWM2 (PCA PWM Mode Auxiliary Register 2)
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
-
-
-
-
-
-
EPC2H
EPC2L
SFR: PCAPWM3 (PCA PWM Mode Auxiliary Register 3)
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
-
-
-
-
-
-
EPC3H
EPC3L
EPCnL := concatenated with CCAPnL, used to control the duty of the PWM output
The bit EPCnL is going to be combined with CCAPnL to form a 9-bit data which will
be compared with PCA counter low byte CL, so to determine the duty of the module-n’s PWM
output.
If
{CL[7:0]}
<
{ EPCnL, CCAPnL[7:0]} , PWM output LOW
else
PWM output HIGH
EPCnH := Reloaded value of EPCnL while CL[7:0] counts from FFH to 00H
44
MPC82x54A Data Sheet
MEGAWIN
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