MPC82L54AS2 参数 Datasheet PDF下载

型号：	MPC82L54AS2
PDF下载：	下载PDF文件查看货源
内容描述：	8位微控制器 [8-bit micro-controller]
分类和应用：	微控制器
文件页数/大小：	74 页 / 1587 K
品牌：	MEGAWIN [ MEGAWIN TECHNOLOGY CO., LTD ]

{ISPAS1, ISPAS0}:= ISP-Address-Start

{0,0}:=

Set the ISP start address 3000_H. (ISP code could take 3.5K bytes)

{0,1}:=

{1,0}:=

Set the ISP start address 3400_H. (ISP code could take 2.5K bytes)

Set the ISP start address 3800_H. (ISP code could take 1.5K bytes)

{1,1}:= (default)

Express no ISP code.

HWBS: = Hardware-Boot-Selector

0:= (default)

Clearing the bit is to configure the device to boot from ISP program after power-up.

1:=

Setting the bit is to configure the device to boot normally from user’s application program

after power-up.

In fact, the boot entrance is determined by register SWBS from SFR ISPCR ignoring the boot

comes from RST-pin press, software-trigger, or power-up. However, if a boot happens and that

boot comes from power-up action, the device will first load the complement of the HWBS to SWBS,

and decides the boot entrance according to the state of bit SWBS. So the HWBS is named

Hardware Boot Selector. It influence on power-up boot, but does not influence on the boot from

RST-pin or software-trigger.

reserved1:= The bit is reserved for afterward user, and should be left at set.

The user must not clear the bit; otherwise, there could be inadvertent effect impacted on the

device.

SB: = Used to decide if the program code will be Scrambled while it is dumped.

0:=

Code dump from Writer is scrambled.

1:= (default)

Code dump from Writer is transparent.

LOCK: = Used to decide if the program code will be Locked against the popular writer.

0:=

Code dumping from Writer is locked.

1:= (default)

Permit code dumping from general Writers.

NVM register: OR1 (Option Register 1):

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

OR1 [7:1]:= Used to set the boundary of IAP memory

The user’s application program can change only the IAP flash memory, not of AP flash memory

itself nor the ISP flash memory. The IAP memory is defined between address scope

OR1 [7:1]*512 and ISP-Address-Start. Setting the OR1 [7:1] 1111111_Bmeans no IAP memory.

NVM register: OR2 (Option Register 2):

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

reserved1

OSCDN

HWBS2

reserved1

reserved1 ENROSC reserved1

reserved1:= The bit is reserved for afterward user, and should be left at set.

MEGAWIN

MPC82x54A Data Sheet

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