Set the clock rate of the SPI as the frequency of the clock source over 64.
Set the clock rate of the SPI as the frequency of the clock source over 128.
{1,1} :=
There are two extra SFRs make relation with SPI application.
SFR: SPIDAT (SPI Data register)
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Data to be transmitted or Data received
The SFR SPIDAT holds the data to be transmitted or the data received.
SFR: SPISTAT (SPI Status register)
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
SPIF
WCOL
-
-
-
-
-
-
SPIF := SPI transfer completion flag.
When a serial transfer finishes, the SPIF bit is set and an interrupt is generated if both the
ESPI (IE.5) bit and the EA (IE.7) bit are set. If SS is an input and is driven low when SPI is
in master mode with SSIG=0, SPIF will also be set to signal the “mode change”. The SPIF
is cleared in software by “writing 1 to this bit”.
WCOL := SPI Write Collision flag
The WCOL bit is set if the SPI data register SPIDAT is written during a data transfer. The
WCOL flag is cleared in software by “writing 1 to this bit”.
Configure the device to Master/Slave mode
SPEN SSIG SS MSTR
Mode
SPI disable
Active Salve
MISO MOSI SPICLK
GPI/O GPI/O GPI/O
output input input
Remark
SPI is disabled.
0
1
1
1
X
0
0
0
X
0
1
0
X
0
0
Selected as slave
Not selected.
Convert from Master to
Slave
InActive Slave Hi-Z
input input
1→0 slave
output input input
1
1
1
0
1
1
1
X
X
1
0
1
Master
Slave
input output output
output input input
input output output
SPICLK depends on CPOL
Slave
Master
Master
MEGAWIN
MPC82x52A Data Sheet
49
MEGAWIN [ MEGAWIN TECHNOLOGY CO., LTD ]
