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MPC82G516AD 参数 Datasheet PDF下载

MPC82G516AD图片预览
型号: MPC82G516AD
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器 [8-bit microcontroller]
分类和应用: 微控制器
文件页数/大小: 144 页 / 1527 K
品牌: MEGAWIN [ MEGAWIN TECHNOLOGY CO., LTD ]
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AUXIP (Address=AEH, Auxiliary Interrupt Priority Register, Reset Value=xx00,0000B)  
7
6
5
4
3
2
1
0
-
-
PKB  
PS2  
PBD  
PPCA  
PADC  
PSPI  
PKB: Keypad interrupt priority bit.  
PS2: UART2 interrupt priority bit.  
PBD: Brownout Detection interrupt priority bit.  
PPCA: PCA interrupt priority bit.  
PADC: ADC interrupt priority bit.  
PSPI: SPI interrupt priority bit.  
AUXIPH (Address=AFH, Auxiliary Interrupt Priority High Register, Reset Value=xx00,0000B)  
7
6
5
4
3
2
1
0
-
-
PKBH  
PS2H  
PBDH  
PPCAH PADCH PSPIH  
PKBH: Keypad interrupt priority bit, high.  
PS2H: UART2 interrupt priority bit, high.  
PBDH: Brownout Detection interrupt priority bit, high.  
PPCAH: PCA interrupt 1 priority bit, high.  
PADCH: ADC interrupt priority bit, high.  
PSPIH: SPI interrupt 0 priority bit, high.  
XICON (Address=C0H, External Interrupt Control Register, Reset Value=0000,0000B)  
7
6
5
4
3
2
1
0
PX3  
EX3  
IE3  
IT3  
PX2  
EX2  
IE2  
IT2  
PX3: External interrupt 3 priority bit.  
EX3: External interrupt 3 enable bit.  
IE3: External interrupt 3 interrupt flag.  
IT3: External interrupt 3 type control bit. 1: edge-triggered; 0: level-triggered.  
PX2: External interrupt 2 priority bit.  
EX2: External interrupt 2 enable bit.  
IE2: External interrupt 2 interrupt flag.  
IT2: External interrupt 2 type control bit. 1: edge-triggered; 0: level-triggered.  
TCON (Address=88H, Timer/Counter Control Register, Reset Value=0000,0000B)  
7
6
5
4
3
2
1
0
TF1  
TR1  
TF0  
TR0  
IE1  
IT1  
IE0  
IT0  
IE1: Interrupt 1 flag. Set by hardware when external interrupt 1 edge is detected (transmitted or level-activated).  
Cleared when interrupt processed only if transition activated.  
IT1: Interrupt 1 Type control bit. Set/cleared by software to specify falling edge/low level triggered external  
interrupt 1.  
IE0: Interrupt 0 flag. Set by hardware when external interrupt 0 edge is detected (transmitted or level-activated).  
Cleared when interrupt processed only if transition activated.  
IT0: Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level triggered external  
interrupt 0.  
MEGAWIN  
MPC82G516A Data Sheet  
92  
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