Typical Timing Diagram
1
2
3
4
5
6
7
8
Clock Cycle
SPICLK(CPOL=0)
Driven from Master
SPICLK(CPOL=1)
Driven from Master
DORD=0 MSB
LSB
6
1
5
2
4
3
3
4
2
5
1
6
MOSI (input)
Driven from Master
DORD=1
LSB
MSB
MOSI turns to input
DORD=0
DORD=1
MSB
LSB
LSB
6
1
5
2
4
3
3
4
2
5
1
6
MISO (output)
MSB
MISO turns to output
SS pin (if SSIG bit = 0 )
Driven from Master
SPI slave transfer format with CPHA=0
1
2
3
4
5
6
7
8
Clock Cycle
SPICLK(CPOL=0)
Driven from Master
SPICLK(CPOL=1)
Driven from Master
DORD=0 MSB
LSB
6
1
5
2
4
3
3
4
2
5
1
6
MOSI (input)
Driven from Master
DORD=1
LSB
MSB
MOSI turns to input
DORD=0
DORD=1
MSB
LSB
LSB
6
1
5
2
4
3
3
4
2
5
1
6
MISO (output)
MSB
MISO turns to output
SS pin (if SSIG bit = 0 )
Driven from Master
SPI slave transfer format with CPHA=1
1
2
3
4
5
6
7
8
Clock Cycle
SPICLK is strongly output-driving.
SPICLK(CPOL=0)
SPICLK(CPOL=1)
SPEN=0 or MSTR=0, MOSI switched not to output
data of SPI communication, also SPICLK is
released from SPI control
SPEN=1 and MSTR=1, MOSI turns to output data
MISO turns to input data
DORD=0
MSB
LSB
6
1
5
2
4
3
3
4
2
5
1
6
MOSI (Output)
LSB
DORD=1
MSB
MOV SPDAT,#data in software
MSB
LSB
DORD=0
DORD=1
LSB
6
1
5
2
4
3
3
4
2
5
1
6
MISO (Input)
Driven from the target slave
MSB
Target slave SS pin
Control GPIO pin by software
SS pin( if SSIG=0)
SPI master transfer format with CPHA=0
52
MPC82x54A Data Sheet
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