CF bit (CCON.7) will be set when the PCA timer overflows, and an interrupt will be generated
if the ECF (CMOD.0) is set. The CF bit can only be cleared by software. There are four bits
named CCF0, CCF1, CCF2 and CCF3 in SFR CCON. Those bits serve as flags for module-0,
module-1, module-2, and module-3 respectively. They are set by hardware when either a
match or a capture occurs. These flags also can only be cleared by software.
Fosc/12
To PCA module
Fosc/2
CH
CL
PCA
interrupt
Timer0 overflow
16-bit counter
External input
ECI (P3.4)
IDLE
-
-
CIDL
-
-
-
CPS1 CPS0 ECF
CMOD
CCON
CCF3 CCF2 CCF1
-
CF
CR
CCF0
PCA Timer/Counter
SFR: CMOD (PCA Counter Mode Register)
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
CIDL
-
-
-
-
CPS1
CPS0
ECF
CIDL:= Behavior control of the PCA.
0:= (default)
Disable counting of the PCA counter while the MCU is put under idle state.
1:=
Enable counting of the PCA counter while the MCU is put under idle state.
{ CPS1, CPS0 }:= Used to select the clocking source for PCA counter
{ 0, 0 }:= set the frequency of the PCA counter clock source as oscillator’s frequency over 12
{ 0, 1 }:= set the frequency of the PCA counter clock source as oscillator’s frequency over 2
{ 1, 0 }:= set the PCA counter clock source as Timer-0 overflow
{ 1, 1 }:= set the PCA counter clock source as pin ECI(pin P3.4)
ECF:= Control bit of deciding if to pass interrupt from PCA timer overflow to the MCU
0:= (default)
Inhibit the interrupt from PCA timer to the MCU
1:=
Permit the interrupt from PCA timer to the MCU
SFR: CCON (PCA Counter Control Register)
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
CF
CR
-
-
CCF3
CCF2
CCF1
CCF0
MEGAWIN
MPC82x54A Data Sheet
39
MEGAWIN [ MEGAWIN TECHNOLOGY CO., LTD ]
