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MPC2F35L 参数 Datasheet PDF下载

MPC2F35L图片预览
型号: MPC2F35L
PDF下载: 下载PDF文件 查看货源
内容描述: 低速USB微控制器 [Low-speed USB micro-controller]
分类和应用: 微控制器
文件页数/大小: 46 页 / 240 K
品牌: MEGAWIN [ MEGAWIN TECHNOLOGY CO., LTD ]
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Interrupt Registers  
IRQ enable flag  
Address  
00C1H  
Name  
Bit 7  
-
Bit 6  
-
Bit 5  
INT1  
Bit 4  
INT0  
Bit 3  
P3  
Bit 2  
TM0  
Bit 1  
USB  
R
W
Bit 0  
-
IRQ_EN  
Program can enable (setting to “1”) or disable (clearing to “0”) the ability of triggering IRQ through this  
register.  
z
z
z
z
USB: USB finishes Rx or Tx data  
TM0: Timer0 underflow  
P3: Falling edge trigger signal occurs at port 3 input mode  
INT0, INT1: Falling edge trigger signal occurs at P0.4 and P0.5 input mode  
IRQ status flag  
Address  
Name  
Bit 7  
-
Bit 6  
-
Bit 5  
INT1  
Bit 4  
INT0  
Bit 3  
P3  
Bit 2  
TM0  
Bit 1  
USB  
R
W
-
Bit 0  
-
00C2H  
IRQ_ST  
When IRQ occurs, program can read this register to know which source triggering IRQ.  
IRQ clear flag  
Address  
00C3H  
Name  
Bit 7  
-
Bit 6  
-
Bit 5  
INT1  
Bit 4  
INT0  
Bit 3  
P3  
Bit 2  
TM0  
Bit 1  
USB  
R
-
W
Bit 0  
-
IRQ_CLR  
Program can clear the interrupt event by writing ‘1’ into the corresponding bit.  
Watchdog Timer (WDT)  
Address  
00DEH  
00DFH  
Name  
Bit 7  
RSTS  
CLR  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 3  
-
Bit 2  
Bit 2  
-
Bit 1  
Bit 1  
-
R
W
-
Bit 0  
Bit 0  
-
WDT_ST  
WDT_CLR  
-
-
-
-
-
-
-
z
z
Bit 3 ~ Bit 0: Contents of WDT  
RSTS: WDT reset status, set by the hardware when WDT overflows, and clear by the firmware or  
the hardware reset  
z
CLR: RSTS clear and WDT reset control bit, the program can clear the RSTS bit and reset WDT  
by writing “1” into the CLR bit  
The watchdog timer (WDT) is organized as a 4-bit counter, which is designed to prevent the program  
from unknown errors. If the WDT overflows, the WDT reset function will be performed. RSTS (Bit 7 of  
WDT_ST) is set by hardware when the WDT overflows. It also can be cleared by hardware reset or  
writing 1 to bit 7 of WDT_CLR. The interval of WDT to cause reset is around 0.7s at 6MHz external  
oscillator. Programming one into the bit 7 of WDT_CLR register can reset the contents of the WDT. In  
normal operation, the application program must reset WDT before it overflows. A WDT overflow  
indicates that operation is not under control and the chip will be reset. The organization of the watchdog  
timer is shown as below  
MEGAWIN  
MPC2F35_USB Data Sheet  
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