MG87FE/L2051/4051/6051
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Preliminary Ver 1.00
12. Analog Comparator
A single analog comparator is provided in the MG87FE/L2051/4051/6051. The comparator operation is such that
the output is a logical “HIGH” when the positive input AIN0 (P1.0]) is greater than the negative input AIN1 (P1.1).
Otherwise the output is “LOW”. Setting the ACEN bit in ACSR enables the comparator. When the comparator is
first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds. The
corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt flag
must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service.
The comparator may be configured to cause an interrupt under a variety of output value conditions by setting the
ACM bits in ACSR. The comparator interrupt flag ACF in ACSR is set whenever the comparator output matches
the condition specified by ACM. The flag may be polled by firmware or may be used to generate an interrupt and
must be cleared by firmware. The analog comparator is always disabled during Idle or Power-down modes.
12.1. Analog Comparator Structure
To CPU read P3.6
+
-
P1.0 (AIN0)
P1.1 (AIN1)
Timer 1 Overflow
CF
Start
Compare
Start
Compare
Comparator Interrupt detecting logic,
example of negative edge comparator interrupt with debounce
Comparator Structure
The comparator output is sampled at every State 4 (S4) of every machine cycle. The conditions on the analog
inputs may be such that the comparator output will toggle excessively. This is especially true if applying slow
moving analog inputs. Three de-bouncing modes are provided to filter out this noise. In de-bouncing mode, the
comparator uses Timer-1 to modulate its sampling time. When a relevant transition occurs, the comparator waits
until two Timer-1 overflows have occurred before re-sampling the output. If the new sample agrees with the
expected value, ACF is set. Otherwise, the event is ignored. The filter may be tuned by adjusting the timeout
period of Timer-1. Because Timer-1 is free running, the de-bouncer must wait for two overflows to guarantee that
the sampling delay is at least 1 timeout period. Therefore, after the initial edge event, the interrupt may occur
between 1 and 2 timeout periods later.
This document information is the intellectual property of Megawin Technology.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
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