Megawin Technology Co., Ltd.
MG87FE/L52
7.2 Option setting:
ROM code lock-option. When read ROM code & always get 0xFF, PAGE-
ERASE and PROGRAM is also disabled.
When enabled, dump ROM code & the data will be scrambled.
LOCK
SB
MOVCL When enabled, the MOVC operation will be disabled at external mode.
HWBS
HWBS2
EN6T
When power-up, MCU will boot from ISP-memory if ISP-memory is configured.
In addition to power-up, the reset from RESET-pin will also force MCU to boot
from ISP-memory if ISP-memory is configured.
MCU 6T/12T mode, MCU will work at 6T mode when this option was enabled.
The gain of oscillator driving capability. Enable this option could help to reduce
EMI and cause the lower power consumption. *note-1
OSCDN
When enabled, The WDTCR register will be initialized to its reset value only by
power-on reset.
FZWDTCR
Note-1: When OSCDN option was enabled, the power consumption could be lower.
7.3 Data RAM Addressing
MG87FE/L52 has internal data RAM that is mapped to three separated segments. The lower
128 bytes of RAM, upper 128 bytes of RAM and 128 bytes Special Function Register(SFR).
Lower 128 bytes of RAM: (addresses 0x00 to 0x7F) are accessed by either direct or indirect
addressing. Upper 128 bytes of RAM: (addresses 0x80 to 0xFF) are accessed only by indirect
addressing (using R0 or R1). The Special Function Registers: (addresses 0x80 to 0xFF) are
accessed only by direct addressing.
While the program counter is spanning over 1FFFh, the device will fetch its program code from
the external memory at once ignoring the /EA pin status. In that case, it will never fetch the
program code from the following embedded flash.
11
Preliminary ver 1.3
Date: 2009-JAN-20
MEGAWIN [ MEGAWIN TECHNOLOGY CO., LTD ]
