MG87FE/L2051/4051/6051
MAKE YOU WIN
Preliminary Ver 1.00
Automatic Address Recognition
Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial
bit stream by using hardware comparison circuit. This feature improves the overhead of software by eliminating
the need in examine every incoming address. This feature is enabled by setting the SM2 bit in SCON. In mode2
and mode3, the receive interrupt flag(RI) will be automatically set when the received byte contains either the
“Given” address or the “Broadcast” address. These two modes require the 9th received bit is a 1 to indicate that
received information is an address and not the data byte.
In mode1, the RI flag will be set if SM2 is enabled and a valid stop bit is received which the stop bit follows the 8
address bits and the information is either a given or Broadcast address.
In mode 0, SM2 is ignored.
Framing Error Detection
Framing Error Detection allows the serial port to check for valid stop bits in modes 1, 2, or3. A missing stop bit
can be caused, for example, by noise on the serial lines, or transmission by two CPUs simultaneously.
If a stop bit is missing, a Framing Error bit FE is set. The FE bit can be checked in software after each reception
to detect communication errors. Once set, the FE bit must be cleared in software. A valid stop bit will not clear
FE.
The FE bit is located in SCON and shares the same bit address as SM0. Control bit SMOD0 in the PCON
register (location PCON.6) determines whether the SM0 or FE bit is accessed. If SMOD0 = 0, then accesses to
SCON.7 are to SM0. IF SMOD0 = 1, then accesses to SCON.7 are to FE.
11.2. UART Register
SCON: Serial port Control Register
Address=98H, read/write, Power On + RESET=0000-0000
7
6
5
4
3
2
1
0
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
Bit 7: FE, Framing Error bit. The SMOD0 bit must be set to enable access to the FE bit.
0: The FE bit is not cleared by valid frames but should be cleared by software.
1: This bit is set by the receiver when an invalid stop bit is detected.
Bit 7: Serial port mode bit 0, (SMOD0 must = 0 to access bit SM0)
Bit 6: Serial port mode bit 1.
SM0
SM1
Mode
Description
shift register
8-bit UART
9-bit UART
9-bit UART
Baud Rate
FSYSCLK/12
variable
FSYSCLK /64 or FSYSCLK /32
variable
0
0
1
1
0
1
0
1
0
1
2
3
Bit 5: Serial port mode bit 2.
0: Disable SM2 function.
1: Enable the automatic address recognition feature in Modes 2 and 3. If SM2=1, RI will not be set unless the
received 9th data bit is 1, indicating an address, and the received byte is a Given or Broadcast address. In
This document information is the intellectual property of Megawin Technology.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
QP-7300-03D
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