MG87FE/L2051/4051/6051
Preliminary, v 1.03
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8. Configurable I/O Ports
8.1.IO Structure
8.1.1.Port1/3/4 GPIO Structure
VDD
VDD
VDD
2 clocks
delay
Weak
Strong
Very weak
Port pin
Port latch data
Input data
By the way, the pull-up resistor is disabled on P10/P11 in default.
8.2.Port1 Register
P1: Port 1 Register
Address=90H, read/write, Power On + RESET=1111-1111
7
6
5
4
3
2
1
0
P17
P16
P15
P14
P13
P12
P11
P10
Bit 7~0: P17~P10 could be set/cleared by CPU. Or it also can be toggled on addressed port channel by
PWM-Timer underflow event in PWM mode.
8.3.Port3 Register
P3: Port 3 Register
Address=B0H, read/write, Power On + RESET=1X11-1111
7
6
5
4
3
2
1
0
P37
P36
P35
P34
P33
P32
P31
P30
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© Megawin Technology Co., Ltd. 2009 All rights reserved.
QP-7300-03D
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