MG87FE/L2051/4051/6051
MAKE YOU WIN
Preliminary Ver 1.00
13. Watch Dog Timer (WDT)
13.1. WDT Structure
1/256
1/128
1/64
1/32
1/16
15-bit timer
1/8
1/4
1/2
8-bit prescalar
Fosc
IDLE
CLRW
WRF
-
ENW
WIDL
PS2 PS1
PS0
WDTCR Register
13.2. WDT Register
WDTCR: Watch-Dog-Timer Control Register
Address=E1H, read/write, Power On + Reset =0x00-0000
7
6
-
5
4
3
2
PS2
1
PS1
0
PS0
WRF
ENW
CLRW
WIDL
Bit 7: WRF, WDT reset flag.
0: This bit should be cleared by software.
1: When WDT overflows, this bit is set by hardware.
Bit 6: Reserved.
Bit 5: ENW. Enable WDT.
0: ENW can not be cleared by software.
1: Enable WDT while it is set.
Bit 4: CLRW. Clear WDT counter.
0: Hardware will automatically clear this bit.
1: Clear WDT to recount while it is set.
This document information is the intellectual property of Megawin Technology.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
QP-7300-03D
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