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MG87FE/L2051/4051/6051
Preliminary, v 1.03
3. Block Diagram
RAM ADDR
Register
RAM256
Flash ROM
Port4 Latch
PWM Timer
Timer0/1
UART
ISP/IAP
XTAL1/P4.3
XTAL2/P4.2
XTAL OSC/
Port4 Driver
Int. OSC
8051 Core
Interrupt
Address
Generator
RESET
RST Logic
+
-
WDT
Port1 Latch
Port3 Latch
Program
Counter
Port1 Driver
Port3 Driver
DPTR
P1.0 ~ P1.7
P3.0 ~ P3.5
P3.7
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Megawin Technology Co., Ltd. 2009 All rights reserved.
QP-7300-03D
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