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MG87FE/L4051 参数 Datasheet PDF下载

MG87FE/L4051图片预览
型号: MG87FE/L4051
PDF下载: 下载PDF文件 查看货源
内容描述: 8位microcontroll [8-bits microcontroll]
分类和应用:
文件页数/大小: 56 页 / 868 K
品牌: MEGAWIN [ MEGAWIN TECHNOLOGY CO., LTD ]
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MG87FE/L2051/4051/6051  
MEGAWIN  
Preliminary, v 1.03  
MAKE YOU WIN  
19. Auxiliary SFRs  
AUXR: Auxiliary Control Register  
Address=8EH, read/write, RESET=0000-0000  
7
6
5
4
3
2
1
0
INT3H  
INT2H  
P15FS  
P14FS  
P13FS  
P12FS  
P11PU  
P10PU  
Bit 7: INT3H, INT3 High/Rising trigger enable.  
0: Remain INT3 triggered on low level or falling edge on P4.2.  
1: Set INT3 triggered on high level or rising edge on P4.2.  
Bit 6: INT2H, INT2 High/Rising trigger enable.  
0: Remain INT2 triggered on low level or falling edge on P4.3.  
1: Set INT2 triggered on high level or rising edge on P4.3.  
Bit 5: P15FS, pin P1.5 function swapped enable.  
0: Pin P1.5 and P3.5 reserves original default function.  
1: Pin P1.5 function is swapped with P3.5/T1. And Pin P3.5 function is swapped by P1.5.  
Bit 4: P14FS, pin P1.4 function swapped enable.  
0: Pin P1.4 and P3.4 reserve original default function.  
1: Pin P1.4 function is swapped with P3.4/T0. And Pin P3.4 function is swapped by P1.4.  
Bit 3: P13FS, pin P1.3 function swapped enable.  
0: Pin P1.3 and P4.3 reserve original default function.  
1: Pin P1.3 function is swapped with P4.3/INT2. And Pin P4.3 function is swapped by P1.3 if internal OSC is  
enabled to release XTAL1 for GPIO function.  
Bit 2: P12FS, pin P1.2 function swapped enable.  
0: Pin P1.2 and P4.2 reserve original default function.  
1: Pin P1.2 function is swapped with P4.2/INT3. And Pin P4.2 function is swapped by P1.2 if internal OSC is  
enabled to release XTAL2 for GPIO function.  
Bit 1: P11PU, Enable P1.1 pull-up resistor.  
0: P1.1 without Pull-Up resistor in open-drain mode.  
1: P1.1 with Pull-Up resistor in open-drain mode.  
Bit 0: P10PU, Enable P1.0 pull-up resistor.  
0: P1.0 without Pull-Up resistor in open-drain mode.  
1: P1.0 with Pull-Up resistor in open-drain mode.  
P1.1 & P1.0 is high-impedance input and N-MOS output without pull-up resistor in default mode. P11PU &  
P10PU in AUXR will enable the pull-up resistor on P1.1/P1.0 individually. If P1.1 & P1.0 are used for GPIO  
function, CPU could not drive low without external pull-up resistor in power down mode when P11PU &  
P10PU are enabled.  
AUXR1: Auxiliary Control Register 1  
Address=A2H, read/write, Power On + RESET=0xxx-0xxx  
7
6
-
5
-
4
-
3
GF2  
2
-
1
-
0
P14FD  
Bit 7: P14FD, Enable P14 output with fast driving.  
This document information is the intellectual property of Megawin Technology.  
© Megawin Technology Co., Ltd. 2009 All rights reserved.  
QP-7300-03D  
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