10.2. Timer 2
Three special function registers, AUXR, T2MOD and T2CON, are related to the operation of Timer 2, as listed
below.
AUXR (Address=8EH, Auxiliary Register)
7
6
5
4
-
3
2
-
1
-
0
-
-
BRADJ0
T2X12
DPS
T2X12: Timer 2 clock source select while C/T2 (T2CON.1)=0 in Capture Mode and Auto-Reload Mode.
Set to select Fosc as the clock source, and clear to select Fosc/12.
T2MOD (Address=C9H, Timer 2 Mode Control register)
7
6
5
4
3
2
-
1
0
-
-
-
-
-
T2OE
DCEN
T2OE: Timer 2 clock-out enable bit: 0 to disable, and 1 to enable.
DCEN: Timer 2 down-counting enable bit: 0 to disable, and 1 to enable.
T2CON (Address=C8H, Timer 2 Control Register)
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/-RL2
TF2:
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either
RCLK=1 or TCLK=1.
EXF2:
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX pin and
EXEN2=1. When Timer 2 interrupt is enabled, EXF2=1 will cause the CPU to vector to the Timer 2 interrupt
routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down mode (DCEN = 1).
RCLK:
Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for it’s receive clock in
modes 1 and 3. RCLK=0 causes Timer 1 overflow to be used for the receive clock.
TCLK:
Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for it’s transmit clock in
modes 1 and 3. TCLK=0 causes Timer 1 overflows to be used for the transmit clock.
EXEN2:
Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative transition
on T2EX pin if Timer 2 is not being used to clock the serial port. EXEN2=0 causes Timer 2 to ignore events at
T2EX pin.
TR2:
Start/stop control for Timer 2. A logic 1 starts the timer.
C/T2:
Timer or counter select. When cleared, select internal timer, when set, select external event counter (falling
edge triggered).
CP/-RL2:
Capture/Reload flag. When set, captures will occur on negative transitions at T2EX pin if EXEN2=1. When
cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX pin when
EXEN2=1. When either RCLK=1 or TCLK=1, this bit is ignored and the timer is forced to auto-reload on Timer 2
overflow.
24
MG84FL54B Data Sheet
MEGAWIN
MEGAWIN [ MEGAWIN TECHNOLOGY CO., LTD ]
