Control Registers Definition
The default value of all the control register is 0 after power on.
Chip Address
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
A02
Bit 1
A01
Bit 0
A00
C_ADDR
Chip address register.
Only the contents of chip address register are same as chip address pin A2, A1 and A0, all command could be
enabled. This function will make the master to connect more than one MA009 easily.
Input Port 0
Name
P0
Bit 7
P07
Bit 6
P06
Bit 5
P05
Bit 4
P04
Bit 3
P03
Bit 2
P02
Bit 1
P01
Bit 0
P00
Port P0 input status register.
Name
P0PR
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
Bit 0
PR00
PR01
Port P0 pull high control register.
P0PR.0: P0.0 ~ P0.3 pull high control, 0: enable (large resistance, 350K), 1: disable
P0PR.1: P0.4 ~ P0.7 pull high control, 0: enable (large resistance, 350K), 1: disable
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
Bit 0
PS00
P0PSR
PS01
Port P0 strong pull high selection register.
P0PSR.0: P0.0 ~ P0.3 strong pull high selection, 0: disable, 1: enable (small resistance, 50K)
P0PSR.1: P0.4 ~ P0.7 strong pull high selection, 0: disable, 1: enable (small resistance, 50K)
Name
P0IEN
Bit 7
IE07
Bit 6
IE06
Bit 5
IE05
Bit 4
IE04
Bit 3
IE03
Bit 2
IE02
Bit 1
IE01
Bit 0
IE00
Port P0 interrupts enable register.
P0IEN.0 ~ P0IEN.7: P0.0 ~ P0.7 falling edge interrupts control, 0: disable, 1: enable
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P0EVT
ST07
ST06
ST05
ST04
ST03
ST02
ST01
ST00
Port P0 interrupts events status register.
When a falling edge signal is occurs in any interrupt enabled (the bit 0 or bit 1 of P0IEN is set to 1) pins of port P0,
the corresponding bit of P0EVT will be set to 1. The interrupt will be generated from the INTB (1!0) pin in this
condition, and the mater (for example, a microcontroller) can read the interrupt status from P0EVT. The master
can send EVTCLR (13H) command to MA009 to clear the P0EVT after the interrupt event is processed. This
MEGAWIN
MA009A Technical Summary
5
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