MDT10P22(DF)
9. Instruction Set
Mnemonic
Operands
Instruction Code
Function
No operation
Operating
Status
010000 00000000 NOP
010000 00000001 CLRWT
010000 00000010 SLEEP
010000 00000011 TMODE
010000 00000100 RET
None
Clear Watchdog timer
Sleep mode
TF, PF
TF, PF
None
None
None
None
Z
0→WT
0→WT, stop OSC
W→TMODE
Stack→PC
W→CPIO r
W→R
Load W to TMODE register
Return
010000 00000rrr
010001 1rrrrrrr
011000 trrrrrrr
111010 iiiiiiii
CPIO R
STWR R
LDR R, t
LDWI I
Control I/O port register
Store W to register
Load register
R→t
Load immediate to W
None
None
I→W
010111 trrrrrrr
SWAPR R, t Swap halves register
[R(0~3)↔R(4~7)]
→t
011001 trrrrrrr
011010 trrrrrrr
INCR R, t Increment register
Z
R + 1→t
R + 1→t
INCRSZ R, t Increment register, skip if
zero
None
011011 trrrrrrr
011100 trrrrrrr
ADDWR R, t Add W and register
C, HC, Z
C, HC, Z
W + R→t
SUBWR R, t Subtract W from register
R ﹣W→t
(R+/W+1→t)
011101 trrrrrrr
011110 trrrrrrr
DECR R, t
Decrement register
Z
R ﹣1→t
R ﹣1→t
DECRSZ R, t Decrement register, skip if
zero
None
010010 trrrrrrr
110100 iiiiiiii
010011 trrrrrrr
110101 iiiiiiii
010100 trrrrrrr
110110 iiiiiiii
ANDWR R, t AND W and register
Z
Z
Z
Z
Z
Z
R ∩ W→t
i ∩ W→W
R ∪ W→t
i ∪ W→W
R ♁ W→t
i ♁ W→W
ANDWI i
IORWR R, t
IORWI i
AND W and immediate
Inclu. OR W and register
Inclu. OR W and immediate
XORWR R, t Exclu. OR W and register
XORWI i
Exclu. OR W and
immediate
011111 trrrrrrr
010110 trrrrrrr
COMR R, t Complement register
Z
/R→t
RRR
R, t
Rotate right register
C
R(n) →R(n-1), C
→R(7), R(0)→C
010101 trrrrrrr
RLR
R, t
Rotate left register
C
R(n)→r(n+1),
C→R(0), R(7)→C
0→W
010000 1xxxxxxx CLRW
Clear working register
Clear register
Bit clear
Z
Z
010001 0rrrrrrr
0000bb brrrrrrr
CLRR
BCR
R
0→R
R, b
None
0→R(b)
This specification are subject to be changed without notice. Any latest information
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P. 9
2007/8 Ver. 1.6
MDTIC [ Micon Design Technology Corporation ]
