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MX29LV400BXBI-70 参数 Datasheet PDF下载

MX29LV400BXBI-70图片预览
型号: MX29LV400BXBI-70
PDF下载: 下载PDF文件 查看货源
内容描述: 4M- BIT [ 512K ×8 / 256K ×16 ]的CMOS单电压3V仅限于Flash存储器 [4M-BIT [512K x 8 / 256K x 16] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY]
分类和应用: 存储
文件页数/大小: 59 页 / 1217 K
品牌: Macronix [ MACRONIX INTERNATIONAL ]
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MX29LV400T/B  
functions of these bits. Q7, RY/BY, and DQ6 each offer  
a method for determining whether a program or erase  
operation is complete or in progress. These three bits  
are discussed first.  
RY/BY:Ready/Busy  
The RY/BY is a dedicated, open-drain output pin that  
indicates whether an Automatic Erase/Program algorithm  
is in progress or complete. The RY/BY status is valid  
after the rising edge of the final WE or CE, whichever  
happens first, in the command sequence. Since RY/BY  
is an open-drain output, several RY/BY pins can be tied  
together in parallel with a pull-up resistor to Vcc.  
Q7: Data Polling  
The Data Polling bit, Q7, indicates to the host sys-tem  
whether an Automatic Algorithm is in progress or com-  
pleted, or whether the device is in Erase Suspend. Data  
Polling is valid after the rising edge of the finalWE pulse  
in the program or erase command sequence.  
If the output is low (Busy), the device is actively erasing  
or programming. (This includes programming in the Erase  
Suspend mode.)If the output is high (Ready), the device  
is ready to read array data (including during the Erase  
Suspend mode), or is in the standby mode.  
During the Automatic Program algorithm, the device out-  
puts on Q7 the complement of the datum programmed  
to Q7.This Q7 status also applies to programming dur-  
ing Er ase Suspend.When the Automatic Program algo-  
rithm is complete, the device outputs the datum pro-  
grammed to Q7.The system must provide the program  
address to read valid status information on Q7. If a pro-  
gram address falls within a protected sector, Data Poll-  
ing on Q7 is active for approximately 1 us, then the de-  
vice returns to reading array data.  
Table 7 shows the outputs for RY/BY during write opera-  
tion.  
Q6:Toggle BIT I  
Toggle Bit I on Q6 indicates whether an Automatic Pro-  
gram or Erase algorithm is in progress or complete, or  
whether the device has entered the Erase Suspend mode.  
Toggle Bit I may be read at any address, and is valid  
after the rising edge of the final WE or CE, whichever  
happens first, in the command sequence(prior to the pro-  
gram or erase operation), and during the sector time-  
out.  
During the Automatic Erase algorithm, Data Polling pro-  
duces a "0" on Q7. When the Automatic Erase algo-  
rithm is complete, or if the device enters the Erase Sus-  
pend mode, Data Polling produces a "1" on Q7. This is  
analogous to the complement/true datum out-put de-  
scribed for the Automatic Program algorithm: the erase  
function changes all the bits in a sector to "1" prior to  
this, the device outputs the "complement,or "0".The  
system must provide an address within any of the sec-  
tors selected for erasure to read valid status information  
on Q7.  
During an Automatic Program or Erase algorithm opera-  
tion, successive read cycles to any address cause Q6  
to toggle.The system may use either OE or CE to con-  
trol the read cycles.When the operation is complete, Q6  
stops toggling.  
After an erase command sequence is written, if all sec-  
tors selected for erasing are protected, Q6 toggles and  
returns to reading array data. If not all selected sectors  
are protected, the Automatic Erase algorithm erases the  
unprotected sectors, and ignores the selected sectors  
that are protected.  
After an erase command sequence is written, if all sec-  
tors selected for erasing are protected, Data Polling on  
Q7 is active for approximately 100 us, then the device  
returns to reading array data. If not all selected sectors  
are protected, the Automatic Erase algorithm erases the  
unprotected sectors, and ignores the selected sectors  
that are protected.  
The system can use Q6 and Q2 together to determine  
whether a sector is actively erasing or is erase sus-  
pended.When the device is actively erasing (that is, the  
Automatic Erase algorithm is in progress), Q6 toggling.  
When the device enters the Erase Suspend mode, Q6  
stops toggling. However, the system must also use Q2  
to determine which sectors are erasing or erase-sus-  
pended. Alternatively, the system can use Q7.  
When the system detects Q7 has changed from the  
complement to true data, it can read valid data at Q7-Q0  
on the following read cycles. This is because Q7 may  
change asynchr onously with Q0-Q6 while Output En-  
able (OE) is asserted low.  
P/N:PM0710  
REV. 1.4, NOV. 23, 2001  
14