MX29LV160C T/B
AUTOMATIC CHIP ERASE TIMING WAVEFORM
matic erase starts. Device outputs 0 during erasure
and 1 after erasure on Q7.(Q6 is for toggle bit;see toggle
bit, Data# Polling, timing waveform)
All data in chip are erased. External erase verification is
not required because data is verified automatically by
internal control circuit. Erasure completion can be veri-
fied by Data# Polling or toggle bit checking after auto-
Figure 6.AUTOMATIC CHIP ERASETIMINGWAVEFORM
Erase Command Sequence(last two cycle)
Read Status Data
VA
tWC
tAS
VA
2AAh
555h
Address
CE#
tAH
tCH
tGHWL
OE#
WE#
tWHWH2
tWP
tCS
tWPH
tDS tDH
In
Progress
55h
10h
Complete
Data
tBUSY
tRB
RY/BY#
tVCS
VCC
Note :
VA=Valid Address for reading status data(see "Write Operation Status").
P/N:PM1186
REV. 1.2, JAN. 19, 2006
32
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