MX29LA129M H/L
PIN CONFIGURATION
56TSOP
PIN DESCRIPTION
SYMBOL PIN NAME
A22
CE1
A21
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
CE0
WP#/ACC
RESET#
A11
A10
A9
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
A0
Byte-Select Address
Address Input
2
WE#
OE#
RY/BY#
Q15
Q7
3
A1~A23
Q0~Q15
4
5
6
Data Inputs/Outputs
7
Q14
Q6
8
CE0~CE2 Chip Enable Input
9
GND
Q13
Q5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
WE#
Write Enable Input
Q12
Q4
OE#
Output Enable Input
VI/O
GND
Q11
Q3
RESET#
Hardware Reset Pin, Active Low
WP#/ACC Hardware Write Protect/Programming
Acceleration input
Q10
Q2
A8
VCC
Q9
GND
A7
RY/BY#
BYTE#
VCC
Read/Busy Output
Q1
A6
Q8
Selects 8 bit or 16 bit mode
+3.0V single power supply
Output Buffer Power (2.7V~3.6V this
input should be tied directly to VCC )
Device Ground
A5
Q0
A4
A0
A3
BYTE#
A23
CE2
A2
A1
VI/O
GND
NC
Pin Not Connected Internally
LOGIC SYMBOL
Chip Enable Truth Table
CE2
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
CE1
VIL
VIL
VIH
VIH
VIL
VIL
VIH
VIH
CE0
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
DEVICE
Enabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Disabled
24
16 or 8
A0-A23
Q0-Q15
CEx
OE#
WE#
RESET#
WP#/ACC
BYTE#
VI/O
RY/BY#
Note:For Single-chip applications, CE2 and CE1 can be
strapped to GND.
P/N:PM1171
REV. 1.0, FEB. 27, 2006
3
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