MX25U4035
MX25U8035
(1) Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP,
CP, SE, BE32K, BE, CE, and WRSR, which are intended to change the device content, should be set every time af-
ter the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes high. (see
Figure 10)
(2) Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high. (see
Figure 11)
The WEL bit is reset by following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Quad Page Program (4PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase 32KB (BE32K) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion
- Continuously program mode (CP) instruction completion
(3) Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC
Manufacturer ID is C2(hex), the memory type ID is 25(hex) as the first-byte device ID, and the individual device ID
of second-byte ID are listed as table of "ID Definitions". (see table 7)
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→ 24-bits ID data out
on SO→ to end RDID operation can use CS# to high at any time during data out. (see Figure 12)
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cy-
cle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.
P/N: PM1394
REV. 1.0, MAR. 09, 2009
17
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