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MX25U4035ZUI-25G 参数 Datasheet PDF下载

MX25U4035ZUI-25G图片预览
型号: MX25U4035ZUI-25G
PDF下载: 下载PDF文件 查看货源
内容描述: 4M- BIT [ ×1 / ×2 / ×4 ] 1.8V的CMOS串行闪存 [4M-BIT [x 1/x 2/x 4] 1.8V CMOS SERIAL FLASH]
分类和应用: 闪存
文件页数/大小: 54 页 / 2237 K
品牌: Macronix [ MACRONIX INTERNATIONAL ]
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MX25U4035  
MX25U8035  
DATA PROTECTION  
The MX25U4035/MX25U8035 is designed to offer protection against accidental erasure or programming caused  
by spurious system level signals that may exist during power transition. During power up the device automatically  
resets the state machine in the standby mode. In addition, with its control register architecture, alteration of the  
memory contents only occurs after successful completion of specific command sequences.  
Valid command length checking: The command length will be checked whether it is at byte base and completed  
on byte boundary.  
Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before  
other command to change data. The WEL bit will return to reset stage under following situation:  
- Power-up  
- Write Disable (WRDI) command completion  
- Write Status Register (WRSR) command completion  
- Page Program (PP) command completion  
- Continuously Program mode (CP) instruction completion  
- Sector Erase (SE) command completion  
- Block Erase 32KB (BE32K) command completion  
- Block Erase (BE) command completion  
- Chip Erase (CE) command completion  
Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from  
writing all commands except Release from deep power down mode command (RDP) and Read Electronic Sig-  
nature command (RES).  
Advanced Security Features: there are some protection and securuity features which protect content from inad-  
vertent write and hostile access.  
I. Block lock protection  
- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected  
as read only. The protected area definition is shown as table of "Protected Area Sizes", the protected areas are  
more flexible which may protect various area by setting value of BP0-BP3 bits.  
Please refer to table of "protected area sizes".  
- The Hardware Proteced Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit.  
If the system goes into four I/O read mode, the feature of HPM will be disabled.  
P/N: PM1394  
REV. 1.0, MAR. 09, 2009  
10