MX25L4006E
REVISION HISTORY
Revision No. Description
Page
P27
Date
MAY/19/2010
0.01
1. Modified "Initial Delivery State" description
2. Modified OTP Capable data from 1 to 0
3. Revised Vcc Supply Minimum Voltage Address Bits
4. Changed wording from DMC to SFDP
5. Changed title from "Advanced Information" to "Preliminary"
6. Corrected Max. Write Status Register Cycle Time
7. Revised SFDP sequence description
1. Removed Preliminary
2. Removed SFDP sequence description & content table
3. Removed Write Status Register Cycle Time in notes
1. Added CS# rising and falling time description
2. Modified tW from 10(typ.)/100(max.) to 5(typ.)/40(max.)
3. Added tSE(max.): 300ms
P21
P21
P4,8,11,19
P4
P40
P19
P4
1.0
1.1
JUL/02/2010
OCT/26/2010
P4,8,11,19
P23,37
P8,23
P23,37
P23,37
P38,39
P13
4. Revised clock time to 86MHz
5. Removed note 2
1.2
1. Modified tVSL from 10us(min.) to 200us(min.)
2. Modified description for RoHS compliance
3. Added 8-USON package
P24
P4,38,39
P4,5,38,39,44
MAR/21/2011
1.3
1. Added Read SFDP (RDSFDP) Mode
P4,8,11,
FEB/10/2012
P19~24,29
P/N: PM1576
REV. 1.3, FEB. 10, 2012
51
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