MX25L4006E
Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCLK
Command
0B
24 BIT ADDRESS
SI
23 22 21
3
2
1
0
High-Z
SO
CS#
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
Dummy Byte
7
6
5
4
3
2
0
1
SI
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
SO
MSB
MSB
MSB
Figure 17. Dual Output Read Mode Sequence (Command 3B)
CS#
0
1
2
3
4
5
6
7
8
9
10 11
30 31 32
39 40 41 42 43
SCLK
8 dummy
cycle
8 Bit Instruction
24 BIT Address
Data Output
data
address
bit23, bit22, bit21...bit0
3B(hex)
dummy
SI/SO0
bit6, bit4, bit2...bit0, bit6, bit4....
High Impedance
data
SO/SO1
bit7, bit5, bit3...bit1, bit7, bit5....
P/N: PM1576
REV. 1.3, FEB. 10, 2012
35
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