16-Bit Latchup Protected Analog to Digital Converter
7809LP
TABLE 1. 7809LP PIN DESCRIPTION
PIN
SYMBOL
DESCRIPTION
21
BUSY
Busy Output. Falls when a conversion is started, and remains LOW until the conversion is com-
pleted and the data is latched into the output shift register. CS or R/C must be HIGH when
BUSY rises, or another conversion will start without time for signal acquisition.
22
PWRD
Power Down Input. If HIGH, conversions are inhibited and power consumption is significantly
reduced. Results from the previous conversions are maintained in the output shift register.
23
24
LPVANA Latchup Protection Analog Supply.
LPVDIG Latchup Protection Digital Supply.
TABLE 2. 7809LP ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
MIN
MAX
UNIT
Analog Inputs
R1IN
R2IN
R3IN
CAP
-25
-25
-25
25
25
25
V
V
V
V
V
ANA + 0.3 AGND2 - 0.3
REF 1
Ground Voltage Differences: DGND, AGND2
-0.3
--
0.3
7
V
V
V
ANA
V
7
V
DIG
V
DIG to V
--
0.3
85
V
°C
ANA
Specified Performance
Digital Inputs
-40
-0.3
-65
V
DIG + 0.3
V
°C
Storage Temperature
TSTG
150
1. Indefinite short to AGND2, momentarily short to V
.
ANA
TABLE 3. 7809LP DC ACCURACY SPECIFICATIONS
(SPECIFIED PERFORMANCE -40 TO +85°C)
PARAMETER
MIN
TYP
MAX
UNIT
Integral Linearity Error
-40 to 85°C
--
--
--
--
±3
±5
LSB 1
Differential Linearity Error
-40 to 85°C
--
--
--
--
-2, 3
-1, 6
LSB
LSB
No Missing Codes 2
Transition Noise 3
Full Scale Error 4,5
15
--
--
1.3
--
--
--
Bits
LSB
%
--
±0.6
±0.6
--
Full Scale Error 4,5 (using ext. 2.5000 V )
--
%
ppm/°C
ref
Full Scale Error Drift
--
±7
01.11.05 Rev 7
All data sheets are subject to change without notice
3
©2005 Maxwell Technologies
All rights reserved.
MAXWELL [ MAXWELL TECHNOLOGIES ]
