14-BIT, 400MSPS DIGITAL-TO-ANALOG Converter
5675
TABLE 1. PINOUT DESCRIPTION
PIN
SYMBOL
DESCRIPTION
19, 41, 46, 47
AGND
AVDD
Analog Negative Supply Voltage (Ground)
Analog Positive Supply Voltage
Full-scale Output Current Bias
External Clock Input
20, 42, 45, 48
39
22
21
BIASJ
CLK
CLKC
Complementory External Clock Input
1, 3, 5, 7, 9, 13, 23
25, 27, 29, 31, 33, 35
D9(13:0)A
LVDS Positive Input, data bits 13 through 0
D13A is most significant data bit (MSB)
D0A is the least significant bit (LSB)
2, 4, 6, 8, 10, 14, 24
26, 28, 30, 32, 34, 36
D(13:0)B
LVDS Positive Input, data bits 13 through 0
D13B is most significant data bit (MSB)
D0B is the least significant bit (LSB)
16, 18
38
DGND
DLLOFF
DVDD
Digital Negative Supply Voltage (Ground)
High = DLL Off / Low = DLL On
Digital Positive Supply Voltage
15, 17
40
EXTIO
Internal reference out put or external reference input. Requires a 0.1uf decou-
pling capacitor to groind when used as reference output.
43
44
37
IOUT1
IOUT2
SLEEP
DAC current output. Full scale when all inputs are set to 1. Connect reference
side DAC load resistors to AVDD
DAC complimentory current output. Full scale when all inputs are set to 0.
Connect reference side DAC load resistors to AVDD
Asynchronous hardware power down input. Active high. Internally pulldown.
1
TABLE 2. 5675 ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
MIN
MAX
UNIT
Supply Voltage Range
AV
-0.3
-0.3
-3.6
-0.3
3.6
3.6
3.6
0.5
V
V
DD
DV
DD
AVDD to DV
V
DD
Voltage between AGND and DGND
CLK, CLKC, SLEEP
--
--
--
--
--
V
-0.3 to DVDD DVDD to 0.3
-0.3 to DVDD DVDD to 0.3
-1.0 to DVDD AVDD to 0.3
-0.3 to DVDD AVDD to 0.3
20
V
Digital input D[13:0]A, D[13:0]B
IOUT1, IOUT2
V
V
EXTIO, BIASJ
V
Peak Input Current (any input)
Peak Total Input Current (any input)
Storage temperature range
mA
mA
°C
-30
-65
150
07.13.04 Rev 1
All data sheets are subject to change without notice
2
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