Mic ro p ro c e s s o r S u p e rvis o ry Circ u it
+5V
R1
R2
100
80
V
= +5V
V
CC
CC
T = +25°C
A
0.1µF CAPACITOR
FROM V TO GND
PFO
PFI
MAX791
OUT
60
40
MAX791
GND
20
0
V-
+5V
PFO
0V
10
100
RESET COMPARATOR OVERDRIVE (mV)
(Reset Threshold Voltage - V
1000
10,000
V
TRIP
V-
0V
)
CC
5 - 1.25 1.25 - V
TRIP
R2
=
R1
NOTE: V IS NEGATIVE
TRIP
Figure 15. Monitoring a Negative Voltage
Figure 16. Maximum Transient Duration without Causing a
Reset Pulse vs. Reset Comparator Overdrive
p a ra tor ove rd rive ). The gra ph shows the ma ximum
Mo n it o rin g a Ne g a t ive Vo lt a g e
pulse width that a negative-going V
transient may
CC
The power-fail comparator can be used to monitor a
negative supply voltage using Figure 15’s circuit. When
the negative supply is valid, PFO is low. When the neg-
ative supply voltage drops, PFO goes high. This cir-
cuit’s accuracy is affected by the PFI threshold toler-
typ ic a lly ha ve without c a us ing a re s e t p uls e to b e
issued. As the amplitude of the transient increases (i.e.,
goes farther below the reset threshold), the maximum
allowable pulse width decreases. Typically, a V tran-
CC
sient that goes 100mV below the reset threshold and
lasts for 40µs or less will not cause a reset pulse to be
issued.
ance, the V voltage, and resistors R1 and R2.
CC
Ba c k u p -Ba t t e ry Re p la c e m e n t
The backup battery may be disconnected while V is
CC
A 100nF bypass capacitor mounted close to the V
CC
above the reset threshold. No precautions are neces-
sary to avoid spurious reset pulses.
pin provides additional transient immunity.
Co n n e c t in g a Tim in g Ca p a c it o r t o S WT
Ne g a t ive -Go in g V
Tra n s ie n t s
CC
SWT is inte rna lly c onne c te d to a ± 100nA c urre nt
source. When a capacitor is connected from SWT to
ground (to select an alternative watchdog timeout peri-
od), the current source charges and discharges the
timing capacitor to create the oscillator that controls the
watchdog timeout period. To prevent timing errors or
oscillator start-up problems, minimize external current
leakage sources at this pin, and locate the capacitor as
close to SWT as possible. The sum of PC board leak-
age + SWT capacitor leakage must be small compared
to ±100nA.
While issuing resets to the µP during power-up, power-
down, and brownout conditions, these supervisors are
relatively immune to short-duration negative-going V
CC
transients (glitches). It is usually undesirable to reset
the µP when V experiences only small glitches.
CC
Figure 16 shows maximum transient duration vs. reset
comparator overdrive, for which reset pulses are not
generated. The graph was produced using negative-
going V pulses, starting at 5V and ending below the
CC
reset threshold by the magnitude indicated (reset com-
16 ______________________________________________________________________________________
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
