Mic ro p ro c e s s o r S u p e rvis o ry Circ u it
+5V
3
V
CC
1
2
µP POWER
µP
VBATT
V
OUT
0.1µF
3.6V
MAX791
15
11
RESET
WDI
RESET
I/O
MAX791
10
16
14
NMI
LOWLINE
INTERRUPT
1/6 74HC04
3
WDPO
WDO
14
CC
9
V
MR
1
2
CLOCK
D
Q
Q
5
CD4013
GND
4
SET RESET
6
V
SS
7
TWO
4
*1µF
CONSECUTIVE
WATCHDOG
FAULT
+5V
INDICATIONS
REACTIVATE
4.7k
*SETS Q HIGH ON POWER-UP
Figure 6. Two consecutive watchdog faults latch the system in reset.
d og -time out p e riod , WDO g oe s low 70ns a fte r the
falling edge of WDPO and remains low until the next
transition at WDI (Figure 5). A flip-flop can force the
system into a hardware shutdown if there are two suc-
cessive watchdog faults (Figure 6). WDO has a 2 x TTL
output characteristic.
mod e ), e xc e s s ive c urre nt will flow from WDO or
WDPO through the protection diode(s) of the CMOS-
logic inputs to ground.
S e le c t in g a n Alt e rn a t ive Wa t c h d o g
Tim e o u t P e rio d
SWT inp ut c ontrols the wa tc hd og -time out p e riod .
Wa t c h d o g -P u ls e Ou t p u t
Connecting SWT to V
selects the internal 1.6sec
OUT
As described in the preceding section, WDPO can be
used as the clock input to an external D flip-flop. Upon
the absence of a watchdog edge or pulse at WDI at the
end of a watchdog-timeout period, WDPO will pulse low
for 1ms. The falling edge of WDPO precedes WDO by
70ns. Since WDO is high when WDPO goes low, the
flip-flop’s Q output remains high as WDO goes low
(Figure 5). If the watchdog timer is not reset by a transi-
tion at WDI, WDO remains low and WDPO clocks a
logic low to the Q output, causing the MAX791 to latch
in reset. If the watchdog timer is reset by a transition at
WDI, WDO g oe s hig h a nd the flip -flop ’s Q outp ut
remains high. Thus, a system shutdown is only caused
by two successive watchdog faults.
watchdog-timeout period. Select an alternative timeout
period by connecting a capacitor between SWT and
GND. Do not leave SWT floating, and do not connect it
to ground. The following formula determines the watch-
dog-timeout period:
Watchdog Timeout Period = 2.1 x (capacitor value
in nF) ms
This formula is valid for capacitance values between
4.7nF a nd 100nF (s e e the Wa tc hd og Time out vs .
Timing Ca p a c itor g ra p h in the Typ ic a l Op e ra ting
Cha ra c te ris tic s ). SWT is inte rna lly c onne c te d to a
±100nA (typ) current source, which charges and dis-
charges the timing capacitor to create the oscillator fre-
quency that sets the watchdog timeout period (see
The internal pull-up resistors associated with WDO and
Conne c ting
a Timing Ca p a c itor to SWT in the
WDPO connect to V . Therefore, do not connect
OUT
Applications Information section).
these outputs directly to CMOS logic that is powered
from V since, in the absence of V (i.e., battery
CC
CC
10 ______________________________________________________________________________________
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
